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Seems fine. - Nilay Vaish On March 28, 2013, 3:32 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1803/ > ----------------------------------------------------------- > > (Updated March 28, 2013, 3:32 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9628:7974addc9132 > --------------------------- > mem: Address mapping with fine-grained channel interleaving > > This patch adds an address mapping scheme where the channel > interleaving takes place on a cache line granularity. It is similar to > the existing RaBaChCo that interleaves on a DRAM page, but should give > higher performance when there is less locality in the address > stream. > > > Diffs > ----- > > src/mem/SimpleDRAM.py 89aa34e10625 > src/mem/simple_dram.cc 89aa34e10625 > > Diff: http://reviews.gem5.org/r/1803/diff/ > > > Testing > ------- > > All regressions pass > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
