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Ship it! Ship It! - Nilay Vaish On March 27, 2013, 7:45 a.m., Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1794/ > ----------------------------------------------------------- > > (Updated March 27, 2013, 7:45 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9578:ca68eed34c57 > --------------------------- > sim: separate nextCycle() and clockEdge() in clockedObjects > > Previously, nextCycle() could return the *current* cycle if the current tick > was > already aligned with the clock edge. This behavior is not only confusing (not > quite what the function name implies), but also caused problems in the > drainResume() function. When exiting/re-entering the sim loop (e.g., to take > checkpoints), the CPUs will drain and resume. Due to the previous behavior of > nextCycle(), the CPU tick events were being rescheduled in the same ticks that > were already processed before draining. This caused divergence from runs that > did not exit/re-entered the sim loop. (Initially a cycle difference, but a > significant impact later on.) > > This patch separates out the two behaviors (nextCycle() and clockEdge()), > uses nextCycle() in drainResume, and uses clockEdge() everywhere else. > Nothing (other than name) should change except for the drainResume timing. > > > Diffs > ----- > > src/cpu/inorder/cpu.cc e6347e559e8f > src/cpu/o3/cpu.cc e6347e559e8f > src/cpu/simple/timing.cc e6347e559e8f > src/dev/arm/hdlcd.cc PRE-CREATION > src/dev/arm/pl111.cc e6347e559e8f > src/mem/bridge.cc e6347e559e8f > src/mem/bus.cc e6347e559e8f > src/mem/ruby/system/RubyMemoryControl.cc e6347e559e8f > src/sim/clocked_object.hh e6347e559e8f > > Diff: http://reviews.gem5.org/r/1794/diff/ > > > Testing > ------- > > > Thanks, > > Ali Saidi > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
