When running multithread program, there is a general problem of non 
determinism. IE depending on the stalling a core will execute a loop different 
numbers of times because of locks being
shared between threads.
Example:

Thread 1 executes a spin lock for 1000 loop iterations because it is
waiting for a lock from Thread 2.  Now if Thread 1 were to stall a
little bit, and lets say that Thread 2 unlocks the lock before Thread 1
spins, then Thread 1 should not execute 1000 loop iterations, but rather
only 0 loop iterations. 

In order to remove the non determinism in the simulation, probably we need to 
stall some thread. Is there a way to stall one thread in gem5?



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Today's Topics:

   1. Cron <m5test@zizzer> /z/m5/regression/do-regression quick
      (Cron Daemon)
   2. Re: Integrating DSENT,    a NoC power/area/delay model into
      gem5's GARNET (Chia-Hsin Owen Chen)


----------------------------------------------------------------------

Message: 1
Date: Thu, 04 Apr 2013 03:06:36 -0400
From: [email protected] (Cron Daemon)
To: [email protected]
Subject: [gem5-dev] Cron <m5test@zizzer>
        /z/m5/regression/do-regression quick
Message-ID: <E1UNeFo-00046s-9z@zizzer>
Content-Type: text/plain; charset=ANSI_X3.4-1968

scons: `build/ALPHA/gem5.debug' is up to date.
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See /z/m5/regression/regress-2013-04-04-03:00:01 for details.



------------------------------

Message: 2
Date: Thu, 4 Apr 2013 11:28:52 -0400
From: Chia-Hsin Owen Chen <[email protected]>
To: [email protected]
Subject: Re: [gem5-dev] Integrating DSENT,      a NoC power/area/delay
        model into gem5's GARNET
Message-ID:
        <CAMoNwFLUN2YDVYiucoMf2W3O5mg0Gp=+ecuvsbp2hzcqcpf...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1

Hi all,

I am trying to convert my code to match the gem5 coding style.

Does anyone know if there is any code beautifier that can be configured to
match the gem5 required coding style? I tried astyle but it still can't
fulfill the requirement.

Thanks,
-Owen


On Wed, Dec 5, 2012 at 1:27 AM, Chia-Hsin Owen Chen
<[email protected]>wrote:

> Hi all,
>
> I am a graduate student at MIT, advised by Li-Shiuan Peh. We have recently
> developed a power/area/delay model for NoCs and incorporate into gem5. This
> tool is added to replace the current NoC power/area model, Orion 2.0.
>
> We validated Orion 2.0 and saw substantial errors compared against
> fabricated chip data and SPICE simulation because many technology
> parameters and scaling factors in Orion 2.0 are way off.
>
> We then developed a completely new NoC power/area/delay model called DSENT
> [NOCS'12] that uses an ASIC-based methodology for modeling. DSENT uses very
> few technology parameters that can be readily estimated, builds a standard
> cell library and sizes these cells subject to timing constraints. It has
> been validated against SPICE and measurements, and we currently provide
> 45nm, 32nm, 22nm, 11nm (Trigate), as well as photonic NoCs.
>
> The integrated DSENT takes router configurations from GARNET. The link
> length between two nodes are calculated in the topology scripts using a
> user-specified tile dimension. The frequency and technology can also be
> specified through python scripts. Currently only the technology parameter
> files still remain as text files.
>
> This work is jointly developed by our group, Prof. Vladimir Stojanovic
> (MIT), and Chen Sun (his student). For more detail of DSENT, please visit
> our website (https://sites.google.com/site/mitdsent/home).
>
> I am going to publish a review request and looking forward to your
> comments!
>
> Thanks,
> -Owen
>


------------------------------

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