> On April 15, 2013, 6:01 p.m., Ali Saidi wrote: > > configs/common/Options.py, line 68 > > <http://reviews.gem5.org/r/1809/diff/1/?file=34747#file34747line68> > > > > because the are defaults all these are going to override the defaults > > in Caches.py when ConfigCaches.py is run. we do this other places, but it's > > good to know and perhaps they should be the same latency as the other > > defaults?
This patch also makes CacheConfig.py to check these options. - Xiangyu ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1809/#review4232 ----------------------------------------------------------- On April 16, 2013, 5:37 p.m., Xiangyu Dong wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1809/ > ----------------------------------------------------------- > > (Updated April 16, 2013, 5:37 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9627:6122d201ff80 > --------------------------- > mem: model data array bank in classic cache > The classic cache does not model data array bank, i.e. if a read/write is > being > serviced by a cache bank, no other requests should be sent to this bank. > This patch models a multi-bank cache. Features include: > 1. detect if the bank interleave granularity is larger than cache line size > 2. add CacheBank debug flag > 3. Differentiate read and write latency > 3a. read latency is still named as hit_latency > 3b. write latency is named as write_latency > 4. Add write_latency, num_banks, bank_itlv_bit into the Python parser > Not modeled in this patch: > Due to the lack of retry mechanism in the cache master port, the access form > the memory side will not be denied if the bank is in service. Instead, the > bank > service time will be extended. This is equivalent to an infinite write buffer > for cache fill operations. > > > Diffs > ----- > > src/mem/cache/cache_impl.hh 6d4158ff7b82 > src/mem/cache/base.cc 6d4158ff7b82 > src/mem/cache/SConscript 6d4158ff7b82 > src/mem/cache/base.hh 6d4158ff7b82 > configs/common/CacheConfig.py 6d4158ff7b82 > configs/common/Caches.py 6d4158ff7b82 > configs/common/Options.py 6d4158ff7b82 > src/mem/cache/BaseCache.py 6d4158ff7b82 > > Diff: http://reviews.gem5.org/r/1809/diff/ > > > Testing > ------- > > > Thanks, > > Xiangyu Dong > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
