changeset 0e15490aad4f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0e15490aad4f
description:
kvm: Add basic support for ARM
Architecture specific limitations:
* LPAE is currently not supported by gem5. We therefore panic if LPAE
is enabled when returning to gem5.
* The co-processor based interface to the architected timer is
unsupported. We can't support this due to limitations in the KVM
API on ARM.
* M5 ops are currently not supported. This requires either a kernel
hack or a memory mapped device that handles the guest<->m5
interface.
diffstat:
SConstruct | 1 +
src/cpu/kvm/ArmKvmCPU.py | 43 ++
src/cpu/kvm/SConscript | 4 +
src/cpu/kvm/arm_cpu.cc | 705 +++++++++++++++++++++++++++++++++++++++++++++++
src/cpu/kvm/arm_cpu.hh | 161 ++++++++++
5 files changed, 914 insertions(+), 0 deletions(-)
diffs (truncated from 946 to 300 lines):
diff -r 06ec4e8fc7cd -r 0e15490aad4f SConstruct
--- a/SConstruct Mon Apr 22 13:20:32 2013 -0400
+++ b/SConstruct Mon Apr 22 13:20:32 2013 -0400
@@ -953,6 +953,7 @@
# Check if the requested target ISA is compatible with the host
def is_isa_kvm_compatible(isa):
isa_comp_table = {
+ "arm" : ( "armv7l" ),
}
try:
import platform
diff -r 06ec4e8fc7cd -r 0e15490aad4f src/cpu/kvm/ArmKvmCPU.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/kvm/ArmKvmCPU.py Mon Apr 22 13:20:32 2013 -0400
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from BaseKvmCPU import BaseKvmCPU
+
+class ArmKvmCPU(BaseKvmCPU):
+ type = 'ArmKvmCPU'
+ cxx_header = "cpu/kvm/arm_cpu.hh"
diff -r 06ec4e8fc7cd -r 0e15490aad4f src/cpu/kvm/SConscript
--- a/src/cpu/kvm/SConscript Mon Apr 22 13:20:32 2013 -0400
+++ b/src/cpu/kvm/SConscript Mon Apr 22 13:20:32 2013 -0400
@@ -48,6 +48,10 @@
Source('perfevent.cc')
Source('timer.cc')
+ if env['TARGET_ISA'] == 'arm':
+ SimObject('ArmKvmCPU.py')
+ Source('arm_cpu.cc')
+
DebugFlag('Kvm', 'Basic KVM Functionality')
DebugFlag('KvmContext', 'KVM/gem5 context synchronization')
DebugFlag('KvmIO', 'KVM MMIO diagnostics')
diff -r 06ec4e8fc7cd -r 0e15490aad4f src/cpu/kvm/arm_cpu.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/kvm/arm_cpu.cc Mon Apr 22 13:20:32 2013 -0400
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include <linux/kvm.h>
+
+#include <algorithm>
+#include <cerrno>
+#include <memory>
+
+#include "arch/registers.hh"
+#include "cpu/kvm/arm_cpu.hh"
+#include "cpu/kvm/base.hh"
+#include "debug/Kvm.hh"
+#include "debug/KvmContext.hh"
+#include "debug/KvmInt.hh"
+
+using namespace ArmISA;
+
+#define EXTRACT_FIELD(val, mask, shift) \
+ (((val) & (mask)) >> (shift))
+
+#define REG_IS_ARM(id) \
+ (((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
+
+#define REG_IS_32BIT(id) \
+ (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
+
+#define REG_IS_64BIT(id) \
+ (((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
+
+#define REG_IS_CP(id, cp) \
+ (((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
+
+#define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
+
+#define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
+#define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
+// HACK: These aren't really defined in any of the headers, so we'll
+// assume some reasonable values for now.
+#define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
+#define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
+
+#define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
+
+
+// There is no constant in the kernel headers defining the mask to use
+// to get the core register index. We'll just do what they do
+// internally.
+#define REG_CORE_IDX(id) \
+ (~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE))
+
+#define REG_CP(id) \
+ EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
+
+#define REG_CRN(id) \
+ EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
+
+#define REG_OPC1(id) \
+ EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
+
+#define REG_CRM(id) \
+ EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
+
+#define REG_OPC2(id) \
+ EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
+
+#define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U32) | \
+ ((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
+ ((crn) << KVM_REG_ARM_32_CRN_SHIFT) | \
+ ((opc1) << KVM_REG_ARM_OPC1_SHIFT) | \
+ ((crm) << KVM_REG_ARM_CRM_SHIFT) | \
+ ((opc2) << KVM_REG_ARM_32_OPC2_SHIFT))
+
+#define REG_CP64(cpnum, opc1, crm) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U64) | \
+ ((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
+ ((opc1) << KVM_REG_ARM_OPC1_SHIFT) | \
+ ((crm) << KVM_REG_ARM_CRM_SHIFT))
+
+#define REG_CORE32(kname) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U32) | \
+ (KVM_REG_ARM_CORE) | \
+ (KVM_REG_ARM_CORE_REG(kname)))
+
+#define REG_VFP32(regno) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U32) | \
+ KVM_REG_ARM_VFP | (regno))
+
+#define REG_VFP64(regno) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U64) | \
+ KVM_REG_ARM_VFP | (regno))
+
+#define REG_DEMUX32(dmxid, val) ( \
+ (KVM_REG_ARM | KVM_REG_SIZE_U32) | \
+ (dmxid) | (val))
+
+// Some of the co-processor registers are invariants and must have the
+// same value on both the host and the guest. We need to keep a list
+// of these to prevent gem5 from fiddling with them on the guest.
+static uint64_t invariant_reg_vector[] = {
+ REG_CP32(15, 0, 0, 0, 0), // MIDR
+ REG_CP32(15, 0, 0, 0, 1), // CTR
+ REG_CP32(15, 0, 0, 0, 2), // TCMTR
+ REG_CP32(15, 0, 0, 0, 3), // TLBTR
+ REG_CP32(15, 0, 0, 0, 6), // REVIDR
+
+ REG_CP32(15, 0, 0, 1, 0), // ID_PFR0
+ REG_CP32(15, 0, 0, 1, 1), // ID_PFR1
+ REG_CP32(15, 0, 0, 1, 2), // ID_DFR0
+ REG_CP32(15, 0, 0, 1, 3), // ID_AFR0
+ REG_CP32(15, 0, 0, 1, 4), // ID_MMFR0
+ REG_CP32(15, 0, 0, 1, 5), // ID_MMFR1
+ REG_CP32(15, 0, 0, 1, 6), // ID_MMFR2
+ REG_CP32(15, 0, 0, 1, 7), // ID_MMFR3
+
+ REG_CP32(15, 0, 0, 2, 0), // ID_ISAR0
+ REG_CP32(15, 0, 0, 2, 1), // ID_ISAR1
+ REG_CP32(15, 0, 0, 2, 2), // ID_ISAR2
+ REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
+ REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
+ REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
+
+ REG_CP32(15, 0, 1, 0, 0), // CSSIDR
+ REG_CP32(15, 0, 1, 0, 1), // CLIDR
+ REG_CP32(15, 0, 1, 0, 7), // AIDR
+
+ REG_VFP32(KVM_REG_ARM_VFP_MVFR0),
+ REG_VFP32(KVM_REG_ARM_VFP_MVFR1),
+ REG_VFP32(KVM_REG_ARM_VFP_FPSID),
+
+ REG_DEMUX32(KVM_REG_ARM_DEMUX_ID_CCSIDR, 0),
+};
+
+const static uint64_t KVM_REG64_TTBR0(REG_CP64(15, 0, 2));
+const static uint64_t KVM_REG64_TTBR1(REG_CP64(15, 1, 2));
+
+#define INTERRUPT_ID(type, vcpu, irq) ( \
+ ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
+ ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
+ ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
+
+#define INTERRUPT_VCPU_IRQ(vcpu) \
+ INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
+
+#define INTERRUPT_VCPU_FIQ(vcpu) \
+ INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
+
+
+#define COUNT_OF(l) (sizeof(l) / sizeof(*l))
+
+const std::set<uint64_t> ArmKvmCPU::invariant_regs(
+ invariant_reg_vector,
+ invariant_reg_vector + COUNT_OF(invariant_reg_vector));
+
+
+ArmKvmCPU::KvmIntRegInfo ArmKvmCPU::kvmIntRegs[] = {
+ { REG_CORE32(usr_regs.ARM_r0), INTREG_R0, "R0" },
+ { REG_CORE32(usr_regs.ARM_r1), INTREG_R1, "R1" },
+ { REG_CORE32(usr_regs.ARM_r2), INTREG_R2, "R2" },
+ { REG_CORE32(usr_regs.ARM_r3), INTREG_R3, "R3" },
+ { REG_CORE32(usr_regs.ARM_r4), INTREG_R4, "R4" },
+ { REG_CORE32(usr_regs.ARM_r5), INTREG_R5, "R5" },
+ { REG_CORE32(usr_regs.ARM_r6), INTREG_R6, "R6" },
+ { REG_CORE32(usr_regs.ARM_r7), INTREG_R7, "R7" },
+ { REG_CORE32(usr_regs.ARM_r8), INTREG_R8, "R8" },
+ { REG_CORE32(usr_regs.ARM_r9), INTREG_R9, "R9" },
+ { REG_CORE32(usr_regs.ARM_r10), INTREG_R10, "R10" },
+ { REG_CORE32(usr_regs.ARM_fp), INTREG_R11, "R11" },
+ { REG_CORE32(usr_regs.ARM_ip), INTREG_R12, "R12" },
+ { REG_CORE32(usr_regs.ARM_sp), INTREG_R13, "R13(USR)" },
+ { REG_CORE32(usr_regs.ARM_lr), INTREG_R14, "R14(USR)" },
+
+ { REG_CORE32(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)" },
+ { REG_CORE32(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)" },
+
+ { REG_CORE32(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)" },
+ { REG_CORE32(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)" },
+
+ { REG_CORE32(und_regs[0]), INTREG_SP_UND, "R13(UND)" },
+ { REG_CORE32(und_regs[1]), INTREG_LR_UND, "R14(UND)" },
+
+ { REG_CORE32(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)" },
+ { REG_CORE32(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)" },
+
+
+ { REG_CORE32(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)" },
+ { REG_CORE32(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)" },
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