changeset 744fb905297c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=744fb905297c
description:
ruby: mesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
diffstat:
configs/ruby/MESI_CMP_directory.py | 6 +-
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 78 +++++++++++++------------
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 49 ++++++++--------
src/mem/protocol/MESI_CMP_directory-dir.sm | 41 ++++++-------
src/mem/protocol/MESI_CMP_directory-dma.sm | 2 +-
5 files changed, 88 insertions(+), 88 deletions(-)
diffs (truncated from 551 to 300 lines):
diff -r df1d9fee32a5 -r 744fb905297c configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Tue May 21 11:32:24 2013 -0500
+++ b/configs/ruby/MESI_CMP_directory.py Tue May 21 11:32:38 2013 -0500
@@ -91,8 +91,8 @@
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
+ L1Icache = l1i_cache,
+ L1Dcache = l1d_cache,
l2_select_num_bits = l2_bits,
send_evictions = (
options.cpu_type == "detailed"),
@@ -132,7 +132,7 @@
l2_cntrl = L2Cache_Controller(version = i,
cntrl_id = cntrl_count,
- L2cacheMemory = l2_cache,
+ L2cache = l2_cache,
ruby_system = ruby_system)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
diff -r df1d9fee32a5 -r 744fb905297c
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue May 21 11:32:24
2013 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue May 21 11:32:38
2013 -0500
@@ -1,6 +1,5 @@
-
/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,8 +28,8 @@
machine(L1Cache, "MESI Directory L1 Cache CMP")
: Sequencer * sequencer,
- CacheMemory * L1IcacheMemory,
- CacheMemory * L1DcacheMemory,
+ CacheMemory * L1Icache,
+ CacheMemory * L1Dcache,
Prefetcher * prefetcher = 'NULL',
int l2_select_num_bits,
Cycles l1_request_latency = 2,
@@ -155,27 +154,27 @@
// inclusive cache returns L1 entries only
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1DcacheMemory[addr]);
+ Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
}
- Entry L1Icache_entry := static_cast(Entry, "pointer",
L1IcacheMemory[addr]);
+ Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
return L1Icache_entry;
}
Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1DcacheMemory[addr]);
+ Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
return L1Dcache_entry;
}
Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Icache_entry := static_cast(Entry, "pointer",
L1IcacheMemory[addr]);
+ Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
return L1Icache_entry;
}
State getState(TBE tbe, Entry cache_entry, Address addr) {
- assert((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == false);
+ assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) ==
false);
if(is_valid(tbe)) {
return tbe.TBEState;
@@ -186,7 +185,7 @@
}
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
- assert((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == false);
+ assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) ==
false);
// MUST CHANGE
if(is_valid(tbe)) {
@@ -294,7 +293,7 @@
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
}
- if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L1Icache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it
// in the L1 so let's see if the L2 has it
trigger(prefetch_request_type_to_event(in_msg.Type),
@@ -303,9 +302,9 @@
} else {
// No room in the L1, so we need to make room in the L1
trigger(Event:L1_Replacement,
- L1IcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
-
L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ L1Icache.cacheProbe(in_msg.LineAddress),
+
getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
+
L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
}
} else {
// Data prefetch
@@ -328,7 +327,7 @@
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
}
- if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in
// the L1 let's see if the L2 has it
trigger(prefetch_request_type_to_event(in_msg.Type),
@@ -337,9 +336,9 @@
} else {
// No room in the L1, so we need to make room in the L1
trigger(Event:L1_Replacement,
- L1DcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
-
L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ L1Dcache.cacheProbe(in_msg.LineAddress),
+
getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
+
L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
}
}
}
@@ -397,7 +396,8 @@
if (in_msg.Type == CoherenceRequestType:INV) {
trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type ==
CoherenceRequestType:UPGRADE) {
+ } else if (in_msg.Type == CoherenceRequestType:GETX ||
+ in_msg.Type == CoherenceRequestType:UPGRADE) {
// upgrade transforms to GETX due to race
trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETS) {
@@ -436,15 +436,16 @@
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
}
- if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it in the L1
so let's see if the L2 has it
+ if (L1Icache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it
+ // in the L1 so let's see if the L2 has it.
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
L1IcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ trigger(Event:L1_Replacement,
L1Icache.cacheProbe(in_msg.LineAddress),
+
getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
}
}
} else {
@@ -465,15 +466,16 @@
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
}
- if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it in the L1
let's see if the L2 has it
+ if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it
+ // in the L1 let's see if the L2 has it.
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
L1DcacheMemory.cacheProbe(in_msg.LineAddress),
-
getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]);
+ trigger(Event:L1_Replacement,
L1Dcache.cacheProbe(in_msg.LineAddress),
+
getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
}
}
}
@@ -846,23 +848,23 @@
}
action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block.
Sets the cache to not present, allowing a replacement in parallel with a
fetch.") {
- if (L1DcacheMemory.isTagPresent(address)) {
- L1DcacheMemory.deallocate(address);
+ if (L1Dcache.isTagPresent(address)) {
+ L1Dcache.deallocate(address);
} else {
- L1IcacheMemory.deallocate(address);
+ L1Icache.deallocate(address);
}
unset_cache_entry();
}
action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag
of block B.") {
if (is_invalid(cache_entry)) {
- set_cache_entry(L1DcacheMemory.allocate(address, new Entry));
+ set_cache_entry(L1Dcache.allocate(address, new Entry));
}
}
action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag
of block B.") {
if (is_invalid(cache_entry)) {
- set_cache_entry(L1IcacheMemory.allocate(address, new Entry));
+ set_cache_entry(L1Icache.allocate(address, new Entry));
}
}
@@ -875,19 +877,19 @@
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
- ++L1IcacheMemory.demand_misses;
+ ++L1Icache.demand_misses;
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++L1IcacheMemory.demand_hits;
+ ++L1Icache.demand_hits;
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
- ++L1DcacheMemory.demand_misses;
+ ++L1Dcache.demand_misses;
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++L1DcacheMemory.demand_hits;
+ ++L1Dcache.demand_hits;
}
action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") {
diff -r df1d9fee32a5 -r 744fb905297c
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue May 21 11:32:24
2013 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue May 21 11:32:38
2013 -0500
@@ -1,6 +1,5 @@
-
/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,7 +32,7 @@
*/
machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cacheMemory,
+ : CacheMemory * L2cache,
Cycles l2_request_latency = 2,
Cycles l2_response_latency = 2,
Cycles to_l1_latency = 1
@@ -76,7 +75,7 @@
MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting
for unblock and data";
MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got
unblock, waiting for data";
MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data,
waiting for unblock";
-
+
}
// EVENTS
@@ -160,7 +159,7 @@
// inclusive cache, returns L2 entries only
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
- return static_cast(Entry, "pointer", L2cacheMemory[addr]);
+ return static_cast(Entry, "pointer", L2cache[addr]);
}
std::string getCoherenceRequestTypeStr(CoherenceRequestType type) {
@@ -372,20 +371,20 @@
in_msg.Requestor, cache_entry),
in_msg.Address, cache_entry, tbe);
} else {
- if (L2cacheMemory.cacheAvail(in_msg.Address)) {
+ if (L2cache.cacheAvail(in_msg.Address)) {
// L2 does't have the line, but we have space for it in the L2
trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address,
in_msg.Requestor,
cache_entry),
in_msg.Address, cache_entry, tbe);
} else {
// No room in the L2, so we need to make room before handling the
request
- Entry L2cache_entry :=
getCacheEntry(L2cacheMemory.cacheProbe(in_msg.Address));
+ Entry L2cache_entry :=
getCacheEntry(L2cache.cacheProbe(in_msg.Address));
if (isDirty(L2cache_entry)) {
- trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.Address),
- L2cache_entry,
L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
+ trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Address),
+ L2cache_entry,
L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
} else {
- trigger(Event:L2_Replacement_clean,
L2cacheMemory.cacheProbe(in_msg.Address),
- L2cache_entry,
L2_TBEs[L2cacheMemory.cacheProbe(in_msg.Address)]);
+ trigger(Event:L2_Replacement_clean,
L2cache.cacheProbe(in_msg.Address),
+ L2cache_entry,
L2_TBEs[L2cache.cacheProbe(in_msg.Address)]);
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