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Review request for Default. Description ------- Changeset 9740:6bbd5dbeb97e --------------------------- sim: Add the notion of clock domains to all ClockedObjects This patch adds the notion of source- and derived-clock domains to the ClockedObjects. As such, all clock information is moved to the clock domain, and the ClockedObjects are grouped into domains. The clock domains are either source domains, with a specific clock period, or derived domains that have a parent domain and a divider (potentially chained). For piece of logic that runs at a derived clock (a ratio of the clock its parent is running at) the necessary derived clock domain is created from its corresponding parent clock domain. For now, the derived clock domain only supports a divider, thus ensuring a lower speed compared to its parent. Multiplier functionality implies a PLL logic that has not been modelled yet (create a separate clock instead). The clock domains should be used as a mechanism to provide a controllable clock source that affects clock for every clocked object lying beneath it. The clock of the domain can (in a future patch) be controlled by a handler responsible for dynamic frequency scaling of the respective clock domains. All the config scripts have been retro-fitted with clock domains. For the System a default SrcClockDomain is created. For CPUs that run at a different speed than the system, there is a seperate clock domain created. This domain incorporates the CPU and the associated caches. As before, Ruby runs under its own clock domain. Diffs ----- configs/common/CacheConfig.py 782b7284de21 configs/common/Simulation.py 782b7284de21 configs/example/fs.py 782b7284de21 configs/example/memtest.py 782b7284de21 configs/example/ruby_direct_test.py 782b7284de21 configs/example/ruby_fs.py 782b7284de21 configs/example/ruby_mem_test.py 782b7284de21 configs/example/ruby_network_test.py 782b7284de21 configs/example/ruby_random_test.py 782b7284de21 configs/example/se.py 782b7284de21 configs/ruby/MESI_CMP_directory.py 782b7284de21 configs/ruby/MI_example.py 782b7284de21 configs/ruby/MOESI_CMP_directory.py 782b7284de21 configs/ruby/MOESI_CMP_token.py 782b7284de21 configs/ruby/MOESI_hammer.py 782b7284de21 configs/ruby/Network_test.py 782b7284de21 configs/ruby/Ruby.py 782b7284de21 src/arch/alpha/AlphaSystem.py 782b7284de21 src/arch/mips/MipsSystem.py 782b7284de21 src/cpu/BaseCPU.py 782b7284de21 src/cpu/dummy_checker.cc 782b7284de21 src/cpu/o3/checker.cc 782b7284de21 src/dev/Ethernet.py 782b7284de21 src/mem/ruby/system/RubyMemoryControl.py 782b7284de21 src/sim/ClockDomain.py PRE-CREATION src/sim/ClockedObject.py 782b7284de21 src/sim/SConscript 782b7284de21 src/sim/clock_domain.hh PRE-CREATION src/sim/clock_domain.cc PRE-CREATION src/sim/clocked_object.hh 782b7284de21 tests/configs/base_config.py 782b7284de21 tests/configs/inorder-timing.py 782b7284de21 tests/configs/memtest-ruby.py 782b7284de21 tests/configs/memtest.py 782b7284de21 tests/configs/o3-timing-checker.py 782b7284de21 tests/configs/o3-timing-mp-ruby.py 782b7284de21 tests/configs/o3-timing-mp.py 782b7284de21 tests/configs/o3-timing-ruby.py 782b7284de21 tests/configs/o3-timing.py 782b7284de21 tests/configs/pc-simple-timing-ruby.py 782b7284de21 tests/configs/rubytest-ruby.py 782b7284de21 tests/configs/simple-atomic-dummychecker.py 782b7284de21 tests/configs/simple-atomic-mp-ruby.py 782b7284de21 tests/configs/simple-atomic-mp.py 782b7284de21 tests/configs/simple-atomic.py 782b7284de21 tests/configs/simple-timing-mp-ruby.py 782b7284de21 tests/configs/simple-timing-mp.py 782b7284de21 tests/configs/simple-timing-ruby.py 782b7284de21 tests/configs/simple-timing.py 782b7284de21 tests/configs/tgen-simple-dram.py 782b7284de21 tests/configs/tgen-simple-mem.py 782b7284de21 tests/configs/twosys-tsunami-simple-atomic.py 782b7284de21 Diff: http://reviews.gem5.org/r/1883/diff/ Testing ------- All regressions pass Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
