changeset 7daeab1685e9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7daeab1685e9
description:
mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.
Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.
diffstat:
configs/common/MemConfig.py | 8 ++--
src/mem/SimpleDRAM.py | 54 +++++++++++++--------------
tests/configs/alpha_generic.py | 2 +-
tests/configs/arm_generic.py | 2 +-
tests/configs/inorder-timing.py | 2 +-
tests/configs/o3-timing-checker.py | 2 +-
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing.py | 2 +-
tests/configs/pc-simple-timing-ruby.py | 2 +-
tests/configs/t1000-simple-atomic.py | 2 +-
tests/configs/tgen-simple-dram.py | 2 +-
tests/configs/twosys-tsunami-simple-atomic.py | 4 +-
tests/configs/x86_generic.py | 2 +-
13 files changed, 42 insertions(+), 44 deletions(-)
diffs (268 lines):
diff -r 3af04c92c9aa -r 7daeab1685e9 configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Thu May 30 12:54:13 2013 -0400
+++ b/configs/common/MemConfig.py Thu May 30 12:54:14 2013 -0400
@@ -50,10 +50,10 @@
# first available memory controller model in the tuple will be used.
_mem_aliases_all = [
("simple_mem", "SimpleMemory"),
- ("ddr3-1600", "SimpleDDR3"),
- ("lpddr2_s4-1066", "SimpleLPDDR2_S4"),
- ("lpddr3-1600", "SimpleLPDDR3"),
- ("wio-200", "SimpleWideIO"),
+ ("ddr3_1600_x64", "DDR3_1600_x64"),
+ ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
+ ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
+ ("wio_200_x128", "WideIO_200_x128"),
]
# Filtered list of aliases. Only aliases for existing memory
diff -r 3af04c92c9aa -r 7daeab1685e9 src/mem/SimpleDRAM.py
--- a/src/mem/SimpleDRAM.py Thu May 30 12:54:13 2013 -0400
+++ b/src/mem/SimpleDRAM.py Thu May 30 12:54:14 2013 -0400
@@ -172,14 +172,13 @@
# burst length for an access derived from peerBlockSize
-# High-level model of a single DDR3 x64 interface (one command and
-# address bus), with default timings based on a DDR3-1600 4 Gbit part,
-# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4
-# configuration.
-class SimpleDDR3(SimpleDRAM):
- # Assuming 64 byte cache lines, use a 2kbyte page size, this
- # depends on the memory density
- lines_per_rowbuffer = 32
+# A single DDR3 x64 interface (one command and address bus), with
+# default timings based on DDR3-1600 4 Gbit parts in an 8x8
+# configuration, which would amount to 4 Gbyte of memory.
+class DDR3_1600_x64(SimpleDRAM):
+ # Assuming 64 byte cache lines, and a 1kbyte page size per module
+ # (this depends on the memory density)
+ lines_per_rowbuffer = 128
# Use two ranks
ranks_per_channel = 2
@@ -192,11 +191,11 @@
tCL = '13.75ns'
tRP = '13.75ns'
- # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4)
+ # Assuming 64 byte cache lines, across an x64
# interface, translates to BL8, 4 clocks @ 800 MHz
tBURST = '5ns'
- # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns
+ # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
tRFC = '300ns'
# DDR3, <=85C, half for >85C
@@ -210,10 +209,10 @@
activation_limit = 4
-# High-level model of a single LPDDR2-S4 x32 interface (one
-# command/address bus), with default timings based on a LPDDR2-1066
-# 4 Gbit part
-class SimpleLPDDR2_S4(SimpleDRAM):
+# A single LPDDR2-S4 x32 interface (one command/address bus), with
+# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
+# configuration.
+class LPDDR2_S4_1066_x32(SimpleDRAM):
# Assuming 64 byte cache lines, use a 1kbyte page size, this
# depends on the memory density
lines_per_rowbuffer = 16
@@ -230,8 +229,8 @@
# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
tCL = '15ns'
- # Pre-charge one bank 15 ns and all banks 18 ns
- tRP = '18ns'
+ # Pre-charge one bank 15 ns (all banks 18 ns)
+ tRP = '15ns'
# Assuming 64 byte cache lines, across a x32 DDR interface
# translates to two BL8, 8 clocks @ 533 MHz. Note that this is a
@@ -249,10 +248,9 @@
tXAW = '50ns'
activation_limit = 4
-# High-level model of a single WideIO x128 interface (one command and
-# address bus), with default timings based on an estimated WIO-200 8
-# Gbit part.
-class SimpleWideIO(SimpleDRAM):
+# A single WideIO x128 interface (one command and address bus), with
+# default timings based on an estimated WIO-200 8 Gbit part.
+class WideIO_200_x128(SimpleDRAM):
# Assuming 64 byte cache lines, use a 4kbyte page size, this
# depends on the memory density
lines_per_rowbuffer = 64
@@ -285,12 +283,12 @@
tXAW = '50ns'
activation_limit = 2
-# High-level model of a single LPDDR3 x32 interface (one
-# command/address bus), with default timings based on a LPDDR3-1600 4
-# Gbit part
-class SimpleLPDDR3(SimpleDRAM):
- # 4 Gb and 8 Gb devices use a 1 kByte page size, so ssuming 64 byte
- # cache lines, that is 16 lines
+# A single LPDDR3 x32 interface (one command/address bus), with
+# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
+# configuration
+class LPDDR3_1600_x32(SimpleDRAM):
+ # 4 Gbit and 8 Gbit devices use a 1 kByte page size, so ssuming 64
+ # byte cache lines, that is 16 lines
lines_per_rowbuffer = 16
# Use a single rank
@@ -305,8 +303,8 @@
# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
tCL = '15ns'
- # Pre-charge one bank 15 ns and all banks 18 ns
- tRP = '18ns'
+ # Pre-charge one bank 15 ns (all banks 18 ns)
+ tRP = '15ns'
# Assuming 64 byte cache lines, across a x32 DDR interface
# translates to two bursts of BL8, 8 clocks @ 800 MHz
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/alpha_generic.py
--- a/tests/configs/alpha_generic.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/alpha_generic.py Thu May 30 12:54:14 2013 -0400
@@ -59,7 +59,7 @@
pass
def create_system(self):
- system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, SimpleDDR3)
+ system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
self.init_system(system)
return system
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/arm_generic.py
--- a/tests/configs/arm_generic.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/arm_generic.py Thu May 30 12:54:14 2013 -0400
@@ -61,7 +61,7 @@
def create_system(self):
system = FSConfig.makeArmSystem(self.mem_mode,
self.machine_type,
- SimpleDDR3,
+ DDR3_1600_x64,
None, False)
# We typically want the simulator to panic if the kernel
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/inorder-timing.py Thu May 30 12:54:14 2013 -0400
@@ -39,7 +39,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/o3-timing-checker.py Thu May 30 12:54:14 2013 -0400
@@ -52,7 +52,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/o3-timing-mp.py Thu May 30 12:54:14 2013 -0400
@@ -36,7 +36,7 @@
# system simulated
system = System(cpu = cpus,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/o3-timing.py Thu May 30 12:54:14 2013 -0400
@@ -41,7 +41,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/pc-simple-timing-ruby.py
--- a/tests/configs/pc-simple-timing-ruby.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/pc-simple-timing-ruby.py Thu May 30 12:54:14 2013 -0400
@@ -55,7 +55,7 @@
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
-system = FSConfig.makeLinuxX86System('timing', SimpleDDR3, options.num_cpus,
+system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
mdesc=mdesc, Ruby=True)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/t1000-simple-atomic.py
--- a/tests/configs/t1000-simple-atomic.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/t1000-simple-atomic.py Thu May 30 12:54:14 2013 -0400
@@ -32,7 +32,7 @@
import FSConfig
cpu = AtomicSimpleCPU(cpu_id=0)
-system = FSConfig.makeSparcSystem('atomic', SimpleDDR3)
+system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/tgen-simple-dram.py
--- a/tests/configs/tgen-simple-dram.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/tgen-simple-dram.py Thu May 30 12:54:14 2013 -0400
@@ -48,7 +48,7 @@
cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
# system simulated
-system = System(cpu = cpu, physmem = SimpleDDR3(),
+system = System(cpu = cpu, physmem = DDR3_1600_x64(),
membus = NoncoherentBus(clock="1GHz", width = 16))
# add a communication monitor
diff -r 3af04c92c9aa -r 7daeab1685e9
tests/configs/twosys-tsunami-simple-atomic.py
--- a/tests/configs/twosys-tsunami-simple-atomic.py Thu May 30 12:54:13
2013 -0400
+++ b/tests/configs/twosys-tsunami-simple-atomic.py Thu May 30 12:54:14
2013 -0400
@@ -32,7 +32,7 @@
from FSConfig import *
from Benchmarks import *
-test_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
@@ -46,7 +46,7 @@
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
diff -r 3af04c92c9aa -r 7daeab1685e9 tests/configs/x86_generic.py
--- a/tests/configs/x86_generic.py Thu May 30 12:54:13 2013 -0400
+++ b/tests/configs/x86_generic.py Thu May 30 12:54:14 2013 -0400
@@ -58,7 +58,7 @@
def create_system(self):
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
- SimpleDDR3,
+ DDR3_1600_x64,
numCPUs=self.num_cpus,
mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
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