changeset 304a37519d11 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=304a37519d11
description:
arch: Create a method to finalize physical addresses
in the TLB
Some architectures (currently only x86) require some fixing-up of
physical addresses after a normal address translation. This is usually
to remap devices such as the APIC, but could be used for other memory
mapped devices as well. When running the CPU in a using hardware
virtualization, we still need to do these address fix-ups before
inserting the request into the memory system. This patch moves this
patch allows that code to be used by such CPUs without doing full
address translations.
diffstat:
src/arch/alpha/tlb.cc | 6 +++++
src/arch/alpha/tlb.hh | 1 +
src/arch/arm/tlb.cc | 6 +++++
src/arch/arm/tlb.hh | 1 +
src/arch/mips/tlb.cc | 6 +++++
src/arch/mips/tlb.hh | 1 +
src/arch/power/tlb.cc | 6 +++++
src/arch/power/tlb.hh | 1 +
src/arch/sparc/tlb.cc | 6 +++++
src/arch/sparc/tlb.hh | 1 +
src/arch/x86/tlb.cc | 61 ++++++++++++++++++++++++++++++--------------------
src/arch/x86/tlb.hh | 16 +++++++++++++
src/sim/tlb.cc | 6 +++++
src/sim/tlb.hh | 17 ++++++++++++++
14 files changed, 110 insertions(+), 25 deletions(-)
diffs (282 lines):
diff -r cc3b8601f582 -r 304a37519d11 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/alpha/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -607,6 +607,12 @@
return NoFault;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
} // namespace AlphaISA
AlphaISA::TLB *
diff -r cc3b8601f582 -r 304a37519d11 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/alpha/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -148,6 +148,7 @@
* translateFunctional stub function for future CheckerCPU support
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
};
} // namespace AlphaISA
diff -r cc3b8601f582 -r 304a37519d11 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/arm/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -94,6 +94,12 @@
return true;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
TlbEntry*
TLB::lookup(Addr va, uint8_t cid, bool functional)
{
diff -r cc3b8601f582 -r 304a37519d11 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/arm/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -207,6 +207,7 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
Fault translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
void drainResume();
diff -r cc3b8601f582 -r 304a37519d11 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/mips/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -346,6 +346,12 @@
return NoFault;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
MipsISA::PTE &
TLB::index(bool advance)
diff -r cc3b8601f582 -r 304a37519d11 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/mips/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -118,6 +118,7 @@
* support the Checker model at the moment.
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);
diff -r cc3b8601f582 -r 304a37519d11 src/arch/power/tlb.cc
--- a/src/arch/power/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/power/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -333,6 +333,12 @@
return NoFault;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
PowerISA::PTE &
TLB::index(bool advance)
{
diff -r cc3b8601f582 -r 304a37519d11 src/arch/power/tlb.hh
--- a/src/arch/power/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/power/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -164,6 +164,7 @@
* supported by Checker at the moment
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
// Checkpointing
void serialize(std::ostream &os);
diff -r cc3b8601f582 -r 304a37519d11 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/sparc/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -848,6 +848,12 @@
return NoFault;
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ return NoFault;
+}
+
Cycles
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
diff -r cc3b8601f582 -r 304a37519d11 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/sparc/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -169,6 +169,7 @@
* does not support the Checker model at the moment
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
diff -r cc3b8601f582 -r 304a37519d11 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/x86/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -226,6 +226,40 @@
}
Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ Addr paddr = req->getPaddr();
+
+ // Check for an access to the local APIC
+ if (FullSystem) {
+ LocalApicBase localApicBase =
+ tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
+ AddrRange apicRange(localApicBase.base * PageBytes,
+ (localApicBase.base + 1) * PageBytes - 1);
+
+ if (apicRange.contains(paddr)) {
+ // The Intel developer's manuals say the below restrictions apply,
+ // but the linux kernel, because of a compiler optimization, breaks
+ // them.
+ /*
+ // Check alignment
+ if (paddr & ((32/8) - 1))
+ return new GeneralProtection(0);
+ // Check access size
+ if (req->getSize() != (32/8))
+ return new GeneralProtection(0);
+ */
+ // Force the access to be uncacheable.
+ req->setFlags(Request::UNCACHEABLE);
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(),
+ paddr - apicRange.start()));
+ }
+ }
+
+ return NoFault;
+}
+
+Fault
TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
Mode mode, bool &delayedResponse, bool timing)
{
@@ -366,31 +400,8 @@
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
req->setPaddr(vaddr);
}
- // Check for an access to the local APIC
- if (FullSystem) {
- LocalApicBase localApicBase =
- tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
- Addr baseAddr = localApicBase.base * PageBytes;
- Addr paddr = req->getPaddr();
- if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
- // The Intel developer's manuals say the below restrictions apply,
- // but the linux kernel, because of a compiler optimization, breaks
- // them.
- /*
- // Check alignment
- if (paddr & ((32/8) - 1))
- return new GeneralProtection(0);
- // Check access size
- if (req->getSize() != (32/8))
- return new GeneralProtection(0);
- */
- // Force the access to be uncacheable.
- req->setFlags(Request::UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->contextId(),
- paddr - baseAddr));
- }
- }
- return NoFault;
+
+ return finalizePhysical(req, tc, mode);
}
Fault
diff -r cc3b8601f582 -r 304a37519d11 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/arch/x86/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -129,6 +129,22 @@
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode
mode);
+ /**
+ * Do post-translation physical address finalization.
+ *
+ * Some addresses, for example requests going to the APIC,
+ * need post-translation updates. Such physical addresses are
+ * remapped into a "magic" part of the physical address space
+ * by this method.
+ *
+ * @param req Request to updated in-place.
+ * @param tc Thread context that created the request.
+ * @param mode Request type (read/write/execute).
+ * @return A fault on failure, NoFault otherwise.
+ */
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
+ Mode mode) const;
+
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
diff -r cc3b8601f582 -r 304a37519d11 src/sim/tlb.cc
--- a/src/sim/tlb.cc Mon Jun 03 13:51:03 2013 +0200
+++ b/src/sim/tlb.cc Mon Jun 03 13:55:41 2013 +0200
@@ -58,6 +58,12 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+GenericTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode)
const
+{
+ return NoFault;
+}
+
void
GenericTLB::demapPage(Addr vaddr, uint64_t asn)
{
diff -r cc3b8601f582 -r 304a37519d11 src/sim/tlb.hh
--- a/src/sim/tlb.hh Mon Jun 03 13:51:03 2013 +0200
+++ b/src/sim/tlb.hh Mon Jun 03 13:55:41 2013 +0200
@@ -124,6 +124,23 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+
+
+ /**
+ * Do post-translation physical address finalization.
+ *
+ * This method is used by some architectures that need
+ * post-translation massaging of physical addresses. For example,
+ * X86 uses this to remap physical addresses in the APIC range to
+ * a range of physical memory not normally available to real x86
+ * implementations.
+ *
+ * @param req Request to updated in-place.
+ * @param tc Thread context that created the request.
+ * @param mode Request type (read/write/execute).
+ * @return A fault on failure, NoFault otherwise.
+ */
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
};
#endif // __ARCH_SPARC_TLB_HH__
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