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Ship it! Ship It! - Ali Saidi On June 3, 2013, 5:34 a.m., Andreas Sandberg wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1890/ > ----------------------------------------------------------- > > (Updated June 3, 2013, 5:34 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9740:d879a42f78c4 > --------------------------- > x86: Fix bug when copying TSC on CPU handover > > The TSC value stored in MISCREG_TSC is actually just an offset from > the current CPU cycle to the actual TSC value. Writes with > side-effects to the TSC subtract the current cycle count before > storing the new value, while reads add the current cycle count. When > switching CPUs, the current value is copied without side-effects. This > works as long as the source and the destination CPUs have the same > clock frequencies. The TSC will jump, sometimes backwards, if they > have different clock frequencies. Most OSes assume the TSC to be > monotonic and break when this happens. > > This changeset makes sure that the TSC is copied with side-effects to > ensure that the offset is updated to match the new CPU. > > > Diffs > ----- > > src/arch/x86/utility.cc 304a37519d11 > > Diff: http://reviews.gem5.org/r/1890/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Sandberg > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
