changeset e039a48eeb99 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e039a48eeb99
description:
x86: Fix bug when copying TSC on CPU handover
The TSC value stored in MISCREG_TSC is actually just an offset from
the current CPU cycle to the actual TSC value. Writes with
side-effects to the TSC subtract the current cycle count before
storing the new value, while reads add the current cycle count. When
switching CPUs, the current value is copied without side-effects. This
works as long as the source and the destination CPUs have the same
clock frequencies. The TSC will jump, sometimes backwards, if they
have different clock frequencies. Most OSes assume the TSC to be
monotonic and break when this happens.
This changeset makes sure that the TSC is copied with side-effects to
ensure that the offset is updated to match the new CPU.
diffstat:
src/arch/x86/utility.cc | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diffs (14 lines):
diff -r 4e1f22617336 -r e039a48eeb99 src/arch/x86/utility.cc
--- a/src/arch/x86/utility.cc Tue Jun 11 09:24:10 2013 +0200
+++ b/src/arch/x86/utility.cc Tue Jun 11 09:24:38 2013 +0200
@@ -209,6 +209,10 @@
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
+ // The TSC has to be updated with side-effects if the CPUs in a
+ // CPU switch have different frequencies.
+ dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
+
dest->getITBPtr()->flushAll();
dest->getDTBPtr()->flushAll();
}
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