----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1922/ -----------------------------------------------------------
(Updated June 13, 2013, 11:04 a.m.) Review request for Default. Changes ------- Update include guard on sim/port.hh (old value was left over from a prior naming scheme I abandoned). Description (updated) ------- Changeset 9757:071a2d97327a --------------------------- sim: unify memory & ethernet port binding mechanisms. Get rid of the ugly special-casing and dynamic casting going on in connectPorts(), and make the port binding mechanism more extensible. This is done by moving the port lookup methods to SimObject and creating a common base Port class from which both the old Port (now MemPort) and EtherInt (which perhaps should be renamed EtherPort) derive. Diffs (updated) ----- src/arch/x86/bios/acpi.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherdevice.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherdevice.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherint.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherint.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherlink.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/dev/etherobject.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/mem/mem_object.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/mem/mem_object.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 src/mem/port.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/mem/port.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 src/python/swig/pyobject.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 src/sim/port.hh PRE-CREATION src/sim/sim_object.hh 0b4a08751b42ac522e296bd1a12408b816068fa1 src/sim/sim_object.cc 0b4a08751b42ac522e296bd1a12408b816068fa1 Diff: http://reviews.gem5.org/r/1922/diff/ Testing ------- Thanks, Steve Reinhardt _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
