changeset f44ff0beb51b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f44ff0beb51b
description:
x86: Initialize the MXCSR register
diffstat:
src/arch/x86/faults.cc | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diffs (12 lines):
diff -r 4574c5123153 -r f44ff0beb51b src/arch/x86/faults.cc
--- a/src/arch/x86/faults.cc Tue Jun 18 16:27:28 2013 +0200
+++ b/src/arch/x86/faults.cc Tue Jun 18 16:28:36 2013 +0200
@@ -268,6 +268,8 @@
tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
+ tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+
// Update the handy M5 Reg.
tc->setMiscReg(MISCREG_M5_REG, 0);
MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev