Hello all, In Gem5, an x86 MOVQ instruction (e.g. MOVQ RBX -> RAX) seems to be decoded into a micro-op with one dest (RAX) and two sources (RAX and RBX). The external gem5 twiki says that x86 MOV is microcoded as "Merge the contents of the Src2 register into the contents of Src1 and put the result into the Dest register." A few questions about this: 1) Any insight onto why it is coded this way? 2) In gem5 timing simulator (e.g. O3CPU), will this result in a register read of RAX (in addition to the register write) when executing the MOVQ?
I am asking because I am implementing dependence tracking and this is creating a false dependency between the MOVQ instruction and the previous writer of its dest. Is there a structural way to spot when this is happening - e.g. it inserts the destination as a "dummy" source to maintain ordering or something, or do I have to special-case single-opcode instructions for this? Mark _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
