changeset 488a71df39bc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=488a71df39bc
description:
ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use
Addr.
Address is an allowed name in slicc even when Address is also being
used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then
thinks
Address is a variable name, not type.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 80 ++++----
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 90 +++++-----
src/mem/protocol/MESI_CMP_directory-dir.sm | 52 ++--
src/mem/protocol/MESI_CMP_directory-dma.sm | 8 +-
src/mem/protocol/MESI_CMP_directory-msg.sm | 12 +-
src/mem/protocol/MI_example-cache.sm | 30 +-
src/mem/protocol/MI_example-dir.sm | 50 ++--
src/mem/protocol/MI_example-msg.sm | 12 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 98 +++++-----
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 212 ++++++++++++------------
src/mem/protocol/MOESI_CMP_directory-dir.sm | 114 ++++++------
src/mem/protocol/MOESI_CMP_directory-dma.sm | 22 +-
src/mem/protocol/MOESI_CMP_directory-msg.sm | 14 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 140 +++++++-------
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 132 +++++++-------
src/mem/protocol/MOESI_CMP_token-dir.sm | 128 +++++++-------
src/mem/protocol/MOESI_CMP_token-msg.sm | 10 +-
src/mem/protocol/MOESI_hammer-cache.sm | 104 +++++-----
src/mem/protocol/MOESI_hammer-dir.sm | 130 +++++++-------
src/mem/protocol/MOESI_hammer-msg.sm | 10 +-
src/mem/protocol/Network_test-cache.sm | 6 +-
src/mem/protocol/Network_test-dir.sm | 6 +-
src/mem/protocol/Network_test-msg.sm | 2 +-
src/mem/protocol/RubySlicc_MemControl.sm | 6 +-
src/mem/ruby/system/RubyMemoryControl.cc | 2 +-
25 files changed, 735 insertions(+), 735 deletions(-)
diffs (truncated from 4604 to 300 lines):
diff -r da0e0df0ba97 -r 488a71df39bc
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue Jun 18 16:36:08
2013 +0200
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue Jun 18 16:58:33
2013 -0500
@@ -125,7 +125,7 @@
// TBE fields
structure(TBE, desc="...") {
- Address Address, desc="Physical address for this TBE";
+ Address Addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="data is dirty";
@@ -348,36 +348,36 @@
// Response IntraChip L1 Network - response msg to this L1 cache
in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank
= 2) {
if (responseIntraChipL1Network_in.isReady()) {
- peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Address") {
+ peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L1_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:DATA) {
- if ((getState(tbe, cache_entry, in_msg.Address) == State:IS ||
- getState(tbe, cache_entry, in_msg.Address) == State:IS_I ||
- getState(tbe, cache_entry, in_msg.Address) == State:PF_IS ||
- getState(tbe, cache_entry, in_msg.Address) == State:PF_IS_I) &&
+ if ((getState(tbe, cache_entry, in_msg.Addr) == State:IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:IS_I ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS_I) &&
machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
- trigger(Event:DataS_fromL1, in_msg.Address, cache_entry, tbe);
+ trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
} else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Data_all_Acks, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
} else {
- trigger(Event:Data, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:ACK) {
if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Ack_all, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
} else {
- trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
}
} else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Address, cache_entry, tbe);
+ trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
} else {
error("Invalid L1 response type");
}
@@ -388,22 +388,22 @@
// Request InterChip network - request from this L1 cache to the shared L2
in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank =
1) {
if(requestIntraChipL1Network_in.isReady()) {
- peek(requestIntraChipL1Network_in, RequestMsg, block_on="Address") {
+ peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") {
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L1_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
if (in_msg.Type == CoherenceRequestType:INV) {
- trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETX ||
in_msg.Type == CoherenceRequestType:UPGRADE) {
// upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
} else {
error("Invalid forwarded request type");
}
@@ -495,7 +495,7 @@
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -513,7 +513,7 @@
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -530,7 +530,7 @@
action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -549,7 +549,7 @@
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
out_msg.Destination.add(
@@ -568,7 +568,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -587,7 +587,7 @@
peek(optionalQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
@@ -609,7 +609,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
enqueue(requestIntraChipL1Network_out, RequestMsg, latency=
l1_request_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:UPGRADE;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -627,7 +627,7 @@
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -641,7 +641,7 @@
action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M
downgrade") {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -656,7 +656,7 @@
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -670,7 +670,7 @@
action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -684,7 +684,7 @@
action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor
(could be L2 or L1)") {
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
@@ -696,7 +696,7 @@
action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -710,7 +710,7 @@
action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
assert(is_valid(tbe));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.DataBlk := tbe.DataBlk;
out_msg.Dirty := tbe.Dirty;
@@ -724,7 +724,7 @@
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
peek(requestIntraChipL1Network_in, RequestMsg) {
enqueue(responseIntraChipL1Network_out, ResponseMsg,
latency=l1_response_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
out_msg.Destination.add(in_msg.Requestor);
@@ -744,7 +744,7 @@
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
enqueue(requestIntraChipL1Network_out, RequestMsg,
latency=l1_response_latency) {
assert(is_valid(cache_entry));
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:PUTX;
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
@@ -761,7 +761,7 @@
action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
@@ -773,7 +773,7 @@
action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Address := address;
+ out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
diff -r da0e0df0ba97 -r 488a71df39bc
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue Jun 18 16:36:08
2013 +0200
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue Jun 18 16:58:33
2013 -0500
@@ -130,7 +130,7 @@
// TBE fields
structure(TBE, desc="...") {
- Address Address, desc="Physical address for this TBE";
+ Address Addr, desc="Physical address for this TBE";
State TBEState, desc="Transient state";
DataBlock DataBlk, desc="Buffer for the data block";
bool Dirty, default="false", desc="Data is Dirty";
@@ -289,17 +289,17 @@
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
if(L1unblockNetwork_in.isReady()) {
peek(L1unblockNetwork_in, ResponseMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L2_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L2_TBEs[in_msg.Addr];
DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
- in_msg.Address, getState(tbe, cache_entry, in_msg.Address),
+ in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
assert(in_msg.Destination.isElement(machineID));
if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
- trigger(Event:Exclusive_Unblock, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
} else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
- trigger(Event:Unblock, in_msg.Address, cache_entry, tbe);
+ trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
} else {
error("unknown unblock message");
}
@@ -313,21 +313,21 @@
peek(responseIntraChipL2Network_in, ResponseMsg) {
// test wether it's from a local L1 or an off chip source
assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L2_TBEs[in_msg.Address];
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L2_TBEs[in_msg.Addr];
if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
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