changeset 915be89faf30 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=915be89faf30
description:
ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the
profiler for
profiling the miss latency of requests made to the cache. The
corrresponding
histograms have been moved to the Sequencer. These are combined
together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses
only.
A particular set of histograms used to use the type GenericMachineType
defined
in one of the protocol files. This patch removes this type. Now,
everything
that relied on this type would use MachineType instead. To do this,
SLICC has
been changed so that multiple machine types can be declared by a
controller
in its preamble.
diffstat:
src/mem/protocol/MI_example-cache.sm | 30 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 55 +--
src/mem/protocol/MOESI_hammer-cache.sm | 57 +--
src/mem/protocol/RubySlicc_ComponentMapping.sm | 1 -
src/mem/protocol/RubySlicc_Exports.sm | 12 -
src/mem/protocol/RubySlicc_Types.sm | 11 +-
src/mem/ruby/common/Histogram.cc | 7 +-
src/mem/ruby/profiler/Profiler.cc | 343 +++++++++++-------------
src/mem/ruby/profiler/Profiler.hh | 37 +--
src/mem/ruby/system/Sequencer.cc | 185 ++++++++----
src/mem/ruby/system/Sequencer.hh | 126 ++++++--
src/mem/slicc/ast/MachineAST.py | 21 +-
src/mem/slicc/parser.py | 8 +-
src/mem/slicc/symbols/Type.py | 36 +-
14 files changed, 472 insertions(+), 457 deletions(-)
diffs (truncated from 1337 to 300 lines):
diff -r 1e364e47b73c -r 915be89faf30 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Mon Jun 24 14:17:22 2013 -0400
+++ b/src/mem/protocol/MI_example-cache.sm Tue Jun 25 00:32:03 2013 -0500
@@ -177,18 +177,6 @@
return getCacheEntry(addr).DataBlk;
}
- GenericMachineType getNondirectHitMachType(MachineID sender) {
- if (machineIDToMachineType(sender) == MachineType:L1Cache) {
- //
- // NOTE direct local hits should not call this
- //
- return GenericMachineType:L1Cache_wCC;
- } else {
- return ConvertMachToGenericMach(machineIDToMachineType(sender));
- }
- }
-
-
// NETWORK PORTS
out_port(requestNetwork_out, RequestMsg, requestFromCache);
@@ -347,36 +335,30 @@
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, false);
}
action(rx_load_hit, "rx", desc="External load completed.") {
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address,
- getNondirectHitMachType(in_msg.Sender),
- cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender));
}
}
action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, false);
}
action(sx_store_hit, "sx", desc="External store completed.") {
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address,
- getNondirectHitMachType(in_msg.Sender),
- cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender));
}
}
diff -r 1e364e47b73c -r 915be89faf30 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Jun 24 14:17:22
2013 -0400
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Jun 25 00:32:03
2013 -0500
@@ -399,26 +399,21 @@
}
}
- GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
+ // NOTE: direct local hits should not call this function
+ bool isExternalHit(Address addr, MachineID sender) {
if (machineIDToMachineType(sender) == MachineType:L1Cache) {
- //
- // NOTE direct local hits should not call this
- //
- return GenericMachineType:L1Cache_wCC;
+ return true;
} else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
- if (sender == (mapAddressToRange(addr,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits))) {
+ if (sender == mapAddressToRange(addr, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits)) {
+ return false;
+ } else {
+ return true;
+ }
+ }
- return GenericMachineType:L2Cache;
- } else {
- return GenericMachineType:L2Cache_wCC;
- }
- } else {
- return ConvertMachToGenericMach(machineIDToMachineType(sender));
- }
+ return true;
}
bool okToIssueStarving(Address addr, MachineID machineID) {
@@ -1289,10 +1284,8 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
- sequencer.readCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
-
+ sequencer.readCallback(address, cache_entry.DataBlk, false,
+ MachineType:L1Cache);
}
action(x_external_load_hit, "x", desc="Notify sequencer the load
completed.") {
@@ -1300,11 +1293,9 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
-
- sequencer.readCallback(address,
- getNondirectHitMachType(address, in_msg.Sender),
- cache_entry.DataBlk);
-
+ sequencer.readCallback(address, cache_entry.DataBlk,
+ isExternalHit(address, in_msg.Sender),
+ machineIDToMachineType(in_msg.Sender));
}
}
@@ -1313,10 +1304,8 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
- sequencer.writeCallback(address,
- GenericMachineType:L1Cache,
- cache_entry.DataBlk);
-
+ sequencer.writeCallback(address, cache_entry.DataBlk, false,
+ MachineType:L1Cache);
cache_entry.Dirty := true;
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
}
@@ -1326,11 +1315,9 @@
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
-
- sequencer.writeCallback(address,
- getNondirectHitMachType(address, in_msg.Sender),
- cache_entry.DataBlk);
-
+ sequencer.writeCallback(address, cache_entry.DataBlk,
+ isExternalHit(address, in_msg.Sender),
+ machineIDToMachineType(in_msg.Sender));
}
cache_entry.Dirty := true;
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
diff -r 1e364e47b73c -r 915be89faf30 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Mon Jun 24 14:17:22 2013 -0400
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue Jun 25 00:32:03 2013 -0500
@@ -33,7 +33,7 @@
* Brad Beckmann
*/
-machine(L1Cache, "AMD Hammer-like protocol")
+machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
: Sequencer * sequencer,
CacheMemory * L1Icache,
CacheMemory * L1Dcache,
@@ -288,24 +288,12 @@
}
}
- GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
- if (machineIDToMachineType(sender) == MachineType:L1Cache) {
- //
- // NOTE direct local hits should not call this
- //
- return GenericMachineType:L1Cache_wCC;
- } else {
- return ConvertMachToGenericMach(machineIDToMachineType(sender));
- }
- }
-
- GenericMachineType testAndClearLocalHit(Entry cache_entry) {
+ MachineType testAndClearLocalHit(Entry cache_entry) {
if (is_valid(cache_entry) && cache_entry.FromL2) {
cache_entry.FromL2 := false;
- return GenericMachineType:L2Cache;
- } else {
- return GenericMachineType:L1Cache;
+ return MachineType:L2Cache;
}
+ return MachineType:L1Cache;
}
bool IsAtomicAccessed(Entry cache_entry) {
@@ -853,8 +841,8 @@
action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address, testAndClearLocalHit(cache_entry),
- cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, false,
+ testAndClearLocalHit(cache_entry));
}
action(hx_external_load_hit, "hx", desc="load required external msgs") {
@@ -863,12 +851,9 @@
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(responseToCache_in, ResponseMsg) {
- sequencer.readCallback(address,
- getNondirectHitMachType(in_msg.Addr,
in_msg.Sender),
- cache_entry.DataBlk,
- tbe.InitialRequestTime,
- tbe.ForwardRequestTime,
- tbe.FirstResponseTime);
+ sequencer.readCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
+ tbe.ForwardRequestTime, tbe.FirstResponseTime);
}
}
@@ -876,8 +861,8 @@
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(mandatoryQueue_in, RubyRequest) {
- sequencer.writeCallback(address, testAndClearLocalHit(cache_entry),
- cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, false,
+ testAndClearLocalHit(cache_entry));
cache_entry.Dirty := true;
if (in_msg.Type == RubyRequestType:ATOMIC) {
@@ -889,7 +874,7 @@
action(hh_flush_hit, "\hf", desc="Notify sequencer that flush completed.") {
assert(is_valid(tbe));
DPRINTF(RubySlicc, "%s\n", tbe.DataBlk);
- sequencer.writeCallback(address, GenericMachineType:L1Cache,tbe.DataBlk);
+ sequencer.writeCallback(address, tbe.DataBlk, false, MachineType:L1Cache);
}
action(sx_external_store_hit, "sx", desc="store required external msgs.") {
@@ -898,12 +883,9 @@
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
peek(responseToCache_in, ResponseMsg) {
- sequencer.writeCallback(address,
- getNondirectHitMachType(address, in_msg.Sender),
- cache_entry.DataBlk,
- tbe.InitialRequestTime,
- tbe.ForwardRequestTime,
- tbe.FirstResponseTime);
+ sequencer.writeCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(in_msg.Sender), tbe.InitialRequestTime,
+ tbe.ForwardRequestTime, tbe.FirstResponseTime);
}
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
cache_entry.Dirty := true;
@@ -914,12 +896,9 @@
assert(is_valid(tbe));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address,
- getNondirectHitMachType(address,
tbe.LastResponder),
- cache_entry.DataBlk,
- tbe.InitialRequestTime,
- tbe.ForwardRequestTime,
- tbe.FirstResponseTime);
+ sequencer.writeCallback(address, cache_entry.DataBlk, true,
+ machineIDToMachineType(tbe.LastResponder), tbe.InitialRequestTime,
+ tbe.ForwardRequestTime, tbe.FirstResponseTime);
cache_entry.Dirty := true;
}
diff -r 1e364e47b73c -r 915be89faf30
src/mem/protocol/RubySlicc_ComponentMapping.sm
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm Mon Jun 24 14:17:22
2013 -0400
+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm Tue Jun 25 00:32:03
2013 -0500
@@ -38,4 +38,3 @@
NodeID machineIDToNodeID(MachineID machID);
NodeID machineIDToVersion(MachineID machID);
MachineType machineIDToMachineType(MachineID machID);
-GenericMachineType ConvertMachToGenericMach(MachineType machType);
diff -r 1e364e47b73c -r 915be89faf30 src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm Mon Jun 24 14:17:22 2013 -0400
+++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Jun 25 00:32:03 2013 -0500
@@ -168,18 +168,6 @@
Default, desc="Replace this with access_types passed to the DMA Ruby
object";
}
-enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL")
{
- L1Cache, desc="L1 Cache Mach";
- L2Cache, desc="L2 Cache Mach";
- L3Cache, desc="L3 Cache Mach";
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