changeset 562bb3ea2b69 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=562bb3ea2b69
description:
        tests: Prune 00.gzip from the regressions

        This patch prunes the 00.gzip regressions with the main motivation
        being that it adds little (or no) coverage and requires a substantial
        amount of run time.

        A complete regression run, including compilation from a clean repo, is
        almost 20% faster(!).

diffstat:

 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini |  249 --
 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr     |    6 -
 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout     |   44 -
 tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt  |  729 -------
 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini      |  549 -----
 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr          |    6 -
 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout          |   44 -
 tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt       |  947 
---------
 tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini  |  124 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr      |    7 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout      |   44 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt   |   93 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini  |  196 --
 tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr      |    6 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout      |   44 -
 tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt   |  443 ----
 tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini        |  581 ------
 tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr            |    2 -
 tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout            |   43 -
 tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt         |  964 
----------
 tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini    |  156 -
 tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr        |    2 -
 tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout        |   43 -
 tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt     |  103 -
 tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini    |  228 --
 tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr        |    2 -
 tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout        |   43 -
 tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt     |  461 ----
 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini      |  549 -----
 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr          |    2 -
 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout          |   43 -
 tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt       |  919 
---------
 tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini  |  124 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr      |    3 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout      |   43 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt   |   63 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini  |  196 --
 tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr      |    2 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout      |   43 -
 tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt   |  431 ----
 tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini        |  573 -----
 tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr            |    2 -
 tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout            |   45 -
 tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt         |  890 
---------
 tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini    |  149 -
 tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr        |    2 -
 tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout        |   44 -
 tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt     |   61 -
 tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini    |  222 --
 tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr        |    2 -
 tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout        |   44 -
 tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt     |  412 ----
 tests/long/se/00.gzip/test.py                                   |   33 -
 53 files changed, 0 insertions(+), 11056 deletions(-)

diffs (truncated from 11294 to 300 lines):

diff -r 03a075377221 -r 562bb3ea2b69 
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini   Thu Jun 
27 05:49:49 2013 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +0000
@@ -1,249 +0,0 @@
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu membus physmem
-boot_osflags=a
-clock=1000
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.cpu]
-type=InOrderCPU
-children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus 
tracer workload
-activity=0
-branchPred=system.cpu.branchPred
-cachePorts=2
-checker=Null
-clock=500
-cpu_id=0
-div16Latency=1
-div16RepeatRate=1
-div24Latency=1
-div24RepeatRate=1
-div32Latency=1
-div32RepeatRate=1
-div8Latency=1
-div8RepeatRate=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-fetchBuffSize=4
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-memBlockSize=64
-multLatency=1
-multRepeatRate=1
-numThreads=1
-profile=0
-progress_interval=0
-stageTracing=false
-stageWidth=4
-switched_out=false
-system=system
-threadModel=SMT
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-predType=tournament
-
-[system.cpu.dcache]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=2
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=262144
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=2
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=131072
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-
-[system.cpu.isa]
-type=AlphaISA
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.l2cache]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-size=2097152
-system=system
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=500
-header_cycles=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.membus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleDRAM
-activation_limit=4
-addr_mapping=openmap
-banks_per_rank=8
-channels=1
-clock=1000
-conf_table_reported=false
-in_addr_map=true
-lines_per_rowbuffer=32
-mem_sched_policy=frfcfs
-null=false
-page_policy=open
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-tBURST=5000
-tCL=13750
-tRCD=13750
-tREFI=7800000
-tRFC=300000
-tRP=13750
-tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_thresh_perc=70
-zero=false
-port=system.membus.master[0]
-
diff -r 03a075377221 -r 562bb3ea2b69 
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr       Thu Jun 
27 05:49:49 2013 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +0000
@@ -1,6 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff -r 03a075377221 -r 562bb3ea2b69 
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout       Thu Jun 
27 05:49:49 2013 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-Redirecting stdout to 
build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout
-Redirecting stderr to 
build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:38
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d 
build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re 
tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
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