changeset ccc428657233 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ccc428657233
description:
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.
As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.
The configs and tests are updated accordingly.
diffstat:
configs/common/Options.py | 4 ++++
configs/example/fs.py | 4 ++++
configs/example/memtest.py | 1 +
configs/example/ruby_direct_test.py | 2 +-
configs/example/ruby_fs.py | 2 ++
configs/example/ruby_mem_test.py | 1 +
configs/example/ruby_network_test.py | 1 +
configs/example/ruby_random_test.py | 1 +
configs/example/se.py | 1 +
configs/splash2/cluster.py | 1 +
configs/splash2/run.py | 1 +
src/sim/System.py | 6 ------
tests/configs/base_config.py | 1 +
tests/configs/inorder-timing.py | 1 +
tests/configs/memtest-ruby.py | 1 +
tests/configs/memtest.py | 1 +
tests/configs/o3-timing-checker.py | 1 +
tests/configs/o3-timing-mp-ruby.py | 1 +
tests/configs/o3-timing-mp.py | 1 +
tests/configs/o3-timing-ruby.py | 1 +
tests/configs/o3-timing.py | 1 +
tests/configs/rubytest-ruby.py | 1 +
tests/configs/simple-atomic-dummychecker.py | 1 +
tests/configs/simple-atomic-mp-ruby.py | 1 +
tests/configs/simple-atomic-mp.py | 2 +-
tests/configs/simple-atomic.py | 1 +
tests/configs/simple-timing-mp-ruby.py | 1 +
tests/configs/simple-timing-mp.py | 1 +
tests/configs/simple-timing-ruby.py | 1 +
tests/configs/simple-timing.py | 1 +
tests/configs/tgen-simple-dram.py | 1 +
tests/configs/tgen-simple-mem.py | 1 +
tests/configs/twosys-tsunami-simple-atomic.py | 2 ++
33 files changed, 40 insertions(+), 8 deletions(-)
diffs (truncated from 392 to 300 lines):
diff -r 233420718e61 -r ccc428657233 configs/common/Options.py
--- a/configs/common/Options.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/common/Options.py Thu Jun 27 05:49:49 2013 -0400
@@ -78,6 +78,10 @@
parser.add_option("--simpoint-interval", type="int", default=10000000,
help="SimPoint interval in num of instructions")
parser.add_option("--clock", action="store", type="string", default='2GHz')
+ parser.add_option("--sys-clock", action="store", type="string",
+ default='1GHz',
+ help = """Top-level clock for blocks running at system
+ speed""")
parser.add_option("--cpu-clock", action="store", type="string",
default='2GHz',
help="Clock for blocks running at CPU speed")
diff -r 233420718e61 -r ccc428657233 configs/example/fs.py
--- a/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
@@ -120,6 +120,8 @@
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
+test_sys.clock = options.sys_clock
+
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
@@ -172,6 +174,8 @@
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
DriveMemClass, bm[1])
+ drive_sys.clock = options.sys_clock
+
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
diff -r 233420718e61 -r ccc428657233 configs/example/memtest.py
--- a/configs/example/memtest.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/memtest.py Thu Jun 27 05:49:49 2013 -0400
@@ -144,6 +144,7 @@
system = System(funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
+system.clock = options.sys_clock
def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
diff -r 233420718e61 -r ccc428657233 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_direct_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -93,7 +93,7 @@
# M5 memory size == Ruby memory size checks
#
system = System(physmem = SimpleMemory())
-
+system.clock = options.sys_clock
#
# Create the ruby random tester
#
diff -r 233420718e61 -r ccc428657233 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_fs.py Thu Jun 27 05:49:49 2013 -0400
@@ -93,6 +93,8 @@
else:
fatal("incapable of building non-alpha or non-x86 full system!")
+system.clock = options.sys_clock
+
if options.kernel is not None:
system.kernel = binary(options.kernel)
diff -r 233420718e61 -r ccc428657233 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_mem_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -108,6 +108,7 @@
funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory())
+system.clock = options.sys_clock
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
diff -r 233420718e61 -r ccc428657233 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_network_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -105,6 +105,7 @@
# create the desired simulated system
system = System(cpu = cpus,
physmem = SimpleMemory())
+system.clock = options.sys_clock
Ruby.create_system(options, system)
diff -r 233420718e61 -r ccc428657233 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_random_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -98,6 +98,7 @@
# M5 memory size == Ruby memory size checks
#
system = System(tester = tester, physmem = SimpleMemory())
+system.clock = options.sys_clock
Ruby.create_system(options, system)
diff -r 233420718e61 -r ccc428657233 configs/example/se.py
--- a/configs/example/se.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/se.py Thu Jun 27 05:49:49 2013 -0400
@@ -160,6 +160,7 @@
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange("512MB")),
mem_mode = test_mem_mode)
+system.clock = options.sys_clock
# Sanity check
if options.fastmem:
diff -r 233420718e61 -r ccc428657233 configs/splash2/cluster.py
--- a/configs/splash2/cluster.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/splash2/cluster.py Thu Jun 27 05:49:49 2013 -0400
@@ -214,6 +214,7 @@
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
physmem = SimpleMemory(),
membus = CoherentBus(clock = busFrequency))
+system.clock = '1GHz'
system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
diff -r 233420718e61 -r ccc428657233 configs/splash2/run.py
--- a/configs/splash2/run.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/splash2/run.py Thu Jun 27 05:49:49 2013 -0400
@@ -199,6 +199,7 @@
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
membus = CoherentBus(clock = busFrequency))
+system.clock = '1GHz'
system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
diff -r 233420718e61 -r ccc428657233 src/sim/System.py
--- a/src/sim/System.py Thu Jun 27 05:49:49 2013 -0400
+++ b/src/sim/System.py Thu Jun 27 05:49:49 2013 -0400
@@ -43,12 +43,6 @@
cxx_header = "sim/system.hh"
system_port = MasterPort("System port")
- # Override the clock from the ClockedObject which looks at the
- # parent clock by default. The 1 GHz default system clock serves
- # as a start for the modules that rely on the parent to provide
- # the clock.
- clock = '1GHz'
-
@classmethod
def export_method_cxx_predecls(cls, code):
code('#include "sim/system.hh"')
diff -r 233420718e61 -r ccc428657233 tests/configs/base_config.py
--- a/tests/configs/base_config.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/base_config.py Thu Jun 27 05:49:49 2013 -0400
@@ -131,6 +131,7 @@
Arguments:
system -- System to initialize.
"""
+ system.clock = '1GHz'
system.cpu = self.create_cpus()
if _have_kvm_support and \
diff -r 233420718e61 -r ccc428657233 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/inorder-timing.py Thu Jun 27 05:49:49 2013 -0400
@@ -42,6 +42,7 @@
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
diff -r 233420718e61 -r ccc428657233 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/memtest-ruby.py Thu Jun 27 05:49:49 2013 -0400
@@ -81,6 +81,7 @@
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
funcbus = NoncoherentBus())
+system.clock = options.sys_clock
Ruby.create_system(options, system)
diff -r 233420718e61 -r ccc428657233 tests/configs/memtest.py
--- a/tests/configs/memtest.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/memtest.py Thu Jun 27 05:49:49 2013 -0400
@@ -40,6 +40,7 @@
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
membus = CoherentBus(width=16))
+system.clock = '1GHz'
# l2cache & bus
system.toL2Bus = CoherentBus(clock="2GHz", width=16)
diff -r 233420718e61 -r ccc428657233 tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/o3-timing-checker.py Thu Jun 27 05:49:49 2013 -0400
@@ -55,6 +55,7 @@
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
diff -r 233420718e61 -r ccc428657233 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/o3-timing-mp-ruby.py Thu Jun 27 05:49:49 2013 -0400
@@ -40,6 +40,7 @@
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
for cpu in cpus:
# create the interrupt controller
diff -r 233420718e61 -r ccc428657233 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/o3-timing-mp.py Thu Jun 27 05:49:49 2013 -0400
@@ -39,6 +39,7 @@
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
diff -r 233420718e61 -r ccc428657233 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/o3-timing-ruby.py Thu Jun 27 05:49:49 2013 -0400
@@ -42,6 +42,7 @@
physmem = ruby_memory,
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
diff -r 233420718e61 -r ccc428657233 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/o3-timing.py Thu Jun 27 05:49:49 2013 -0400
@@ -44,6 +44,7 @@
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
diff -r 233420718e61 -r ccc428657233 tests/configs/rubytest-ruby.py
--- a/tests/configs/rubytest-ruby.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/rubytest-ruby.py Thu Jun 27 05:49:49 2013 -0400
@@ -78,6 +78,7 @@
wakeup_frequency = 10, num_cpus = options.num_cpus)
system = System(tester = tester, physmem = SimpleMemory(null = True))
+system.clock = options.sys_clock
Ruby.create_system(options, system)
diff -r 233420718e61 -r ccc428657233 tests/configs/simple-atomic-dummychecker.py
--- a/tests/configs/simple-atomic-dummychecker.py Thu Jun 27 05:49:49
2013 -0400
+++ b/tests/configs/simple-atomic-dummychecker.py Thu Jun 27 05:49:49
2013 -0400
@@ -41,6 +41,7 @@
system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = SimpleMemory(),
membus = CoherentBus())
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
system.cpu.addCheckerCpu()
diff -r 233420718e61 -r ccc428657233 tests/configs/simple-atomic-mp-ruby.py
--- a/tests/configs/simple-atomic-mp-ruby.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/simple-atomic-mp-ruby.py Thu Jun 27 05:49:49 2013 -0400
@@ -39,6 +39,7 @@
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system.clock = '1GHz'
# add L1 caches
for cpu in cpus:
diff -r 233420718e61 -r ccc428657233 tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/simple-atomic-mp.py Thu Jun 27 05:49:49 2013 -0400
@@ -38,7 +38,7 @@
system = System(cpu = cpus,
physmem = SimpleMemory(range = AddrRange('1024MB')),
membus = CoherentBus())
-
+system.clock = '1GHz'
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
diff -r 233420718e61 -r ccc428657233 tests/configs/simple-atomic.py
--- a/tests/configs/simple-atomic.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/simple-atomic.py Thu Jun 27 05:49:49 2013 -0400
@@ -32,6 +32,7 @@
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