changeset 6e6cefc1db1f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6e6cefc1db1f
description:
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
diffstat:
configs/common/CacheConfig.py | 7 +-
configs/common/Simulation.py | 10 +-
configs/example/fs.py | 24 ++-
configs/example/memtest.py | 4 +-
configs/example/ruby_direct_test.py | 8 +-
configs/example/ruby_fs.py | 12 +-
configs/example/ruby_mem_test.py | 7 +-
configs/example/ruby_network_test.py | 7 +-
configs/example/ruby_random_test.py | 7 +-
configs/example/se.py | 15 +-
configs/ruby/MESI_CMP_directory.py | 13 +-
configs/ruby/MI_example.py | 13 +-
configs/ruby/MOESI_CMP_directory.py | 13 +-
configs/ruby/MOESI_CMP_token.py | 13 +-
configs/ruby/MOESI_hammer.py | 13 +-
configs/ruby/Network_test.py | 13 +-
configs/ruby/Ruby.py | 3 +-
src/arch/alpha/AlphaSystem.py | 2 +-
src/arch/mips/MipsSystem.py | 2 +-
src/cpu/BaseCPU.py | 6 +-
src/cpu/dummy_checker.cc | 2 +-
src/cpu/o3/checker.cc | 2 +-
src/dev/Ethernet.py | 5 -
src/mem/ruby/system/RubyMemoryControl.py | 2 -
src/sim/ClockDomain.py | 60 +++++++++
src/sim/ClockedObject.py | 7 +-
src/sim/SConscript | 3 +
src/sim/clock_domain.cc | 118 +++++++++++++++++++
src/sim/clock_domain.hh | 160 ++++++++++++++++++++++++++
src/sim/clocked_object.hh | 40 +++--
tests/configs/base_config.py | 30 +++-
tests/configs/memtest-ruby.py | 17 ++-
tests/configs/memtest.py | 17 +-
tests/configs/o3-timing-mp-ruby.py | 11 +-
tests/configs/o3-timing-ruby.py | 10 +-
tests/configs/pc-simple-timing-ruby.py | 8 +-
tests/configs/rubytest-ruby.py | 7 +-
tests/configs/simple-atomic-mp-ruby.py | 11 +-
tests/configs/simple-timing-mp-ruby.py | 11 +-
tests/configs/simple-timing-ruby.py | 11 +-
tests/configs/tgen-simple-dram.py | 4 +-
tests/configs/tgen-simple-mem.py | 4 +-
tests/configs/twosys-tsunami-simple-atomic.py | 26 +++-
43 files changed, 636 insertions(+), 122 deletions(-)
diffs (truncated from 1486 to 300 lines):
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/common/CacheConfig.py Thu Jun 27 05:49:49 2013 -0400
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -64,12 +64,13 @@
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
- system.l2 = l2_cache_class(clock=options.cpu_clock,
+ system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc,
block_size=options.cacheline_size)
- system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32)
+ system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
+ width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/common/Simulation.py
--- a/configs/common/Simulation.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/common/Simulation.py Thu Jun 27 05:49:49 2013 -0400
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -308,7 +308,7 @@
testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
switch_cpus[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
- switch_cpus[i].clock = testsys.cpu[i].clock
+ switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
# simulation period
if options.maxinsts:
switch_cpus[i].max_insts_any_thread = options.maxinsts
@@ -335,7 +335,7 @@
for i in xrange(np):
repeat_switch_cpus[i].system = testsys
repeat_switch_cpus[i].workload = testsys.cpu[i].workload
- repeat_switch_cpus[i].clock = testsys.cpu[i].clock
+ repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
if options.maxinsts:
repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts
@@ -363,8 +363,8 @@
switch_cpus_1[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus_1[i].workload = testsys.cpu[i].workload
- switch_cpus[i].clock = testsys.cpu[i].clock
- switch_cpus_1[i].clock = testsys.cpu[i].clock
+ switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
+ switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain
# if restoring, make atomic cpu simulate only a few instructions
if options.checkpoint_restore != None:
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/fs.py
--- a/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2012 ARM Limited
+# Copyright (c) 2010-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -81,9 +81,6 @@
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-TestCPUClass.clock = options.cpu_clock
-DriveCPUClass.clock = options.cpu_clock
-
# Match the memories with the CPUs, the driver system always simple,
# and based on the options for the test system
DriveMemClass = SimpleMemory
@@ -120,7 +117,11 @@
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
-test_sys.clock = options.sys_clock
+# Create a source clock for the system and set the clock period
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+
+# Create a source clock for the CPUs and set the clock period
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
@@ -130,7 +131,9 @@
test_sys.init_param = options.init_param
-test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
+# For now, assign all the CPUs to the same clock domain
+test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
+ for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
@@ -174,9 +177,14 @@
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
DriveMemClass, bm[1])
- drive_sys.clock = options.sys_clock
+ # Create a source clock for the system and set the clock period
+ drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
- drive_sys.cpu = DriveCPUClass(cpu_id=0)
+ # Create a source clock for the CPUs and set the clock period
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
+ drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
+ cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/memtest.py
--- a/configs/example/memtest.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/memtest.py Thu Jun 27 05:49:49 2013 -0400
@@ -144,14 +144,14 @@
system = System(funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = CoherentBus(clock="500MHz", width=16)
+ new_bus = CoherentBus(width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_direct_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -92,8 +92,9 @@
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
#
# Create the ruby random tester
#
@@ -103,6 +104,9 @@
Ruby.create_system(options, system)
+# Since Ruby runs at an independent frequency, create a seperate clock
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for ruby_port in system.ruby._cpu_ruby_ports:
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_fs.py Thu Jun 27 05:49:49 2013 -0400
@@ -80,8 +80,6 @@
sys.exit(1)
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
-
TestMemClass = Simulation.setMemClass(options)
if buildEnv['TARGET_ISA'] == "alpha":
@@ -93,7 +91,7 @@
else:
fatal("incapable of building non-alpha or non-x86 full system!")
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
if options.kernel is not None:
system.kernel = binary(options.kernel)
@@ -102,12 +100,20 @@
system.readfile = options.script
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
+
+# Create a source clock for the CPUs and set the clock period
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
Ruby.create_system(options, system, system.piobus, system._dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
+ cpu.clk_domain = system.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_mem_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -107,8 +107,8 @@
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
@@ -129,6 +129,9 @@
dma_ports.append(dma.test)
Ruby.create_system(options, system, dma_ports = dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_network_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -104,11 +104,14 @@
# create the desired simulated system
system = System(cpu = cpus,
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
i = 0
for ruby_port in system.ruby._cpu_ruby_ports:
#
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/ruby_random_test.py Thu Jun 27 05:49:49 2013 -0400
@@ -97,11 +97,14 @@
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(tester = tester, physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(tester = tester, physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
tester.num_cpus = len(system.ruby._cpu_ruby_ports)
diff -r c02004c2cc5b -r 6e6cefc1db1f configs/example/se.py
--- a/configs/example/se.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/se.py Thu Jun 27 05:49:49 2013 -0400
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -147,7 +147,6 @@
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
CPUClass.numThreads = numThreads
MemClass = Simulation.setMemClass(options)
@@ -159,8 +158,16 @@
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange("512MB")),
- mem_mode = test_mem_mode)
-system.clock = options.sys_clock
+ mem_mode = test_mem_mode,
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
