changeset 485399270ca1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=485399270ca1
description:
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.
The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.
The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.
diffstat:
src/mem/cache/BaseCache.py | 5 +-
src/mem/cache/base.cc | 18 ++++--
src/mem/cache/cache.hh | 2 +-
src/mem/cache/cache_impl.hh | 11 +--
src/mem/cache/tags/SConscript | 3 +-
src/mem/cache/tags/Tags.py | 65 ++++++++++++++++++++++++++
src/mem/cache/tags/base.cc | 37 ++++++++++----
src/mem/cache/tags/base.hh | 35 ++++++-------
src/mem/cache/tags/cacheset.cc | 92 ------------------------------------
src/mem/cache/tags/cacheset.hh | 102 ++++++++++++++++++++++++++++++++++++++--
src/mem/cache/tags/fa_lru.cc | 35 ++++++++++---
src/mem/cache/tags/fa_lru.hh | 23 +++-----
src/mem/cache/tags/lru.cc | 22 +++++---
src/mem/cache/tags/lru.hh | 33 ++++++------
14 files changed, 291 insertions(+), 192 deletions(-)
diffs (truncated from 907 to 300 lines):
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/BaseCache.py Thu Jun 27 05:49:50 2013 -0400
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -42,7 +42,7 @@
from m5.proxy import *
from MemObject import MemObject
from Prefetcher import BasePrefetcher
-
+from Tags import *
class BaseCache(MemObject):
type = 'BaseCache'
@@ -70,3 +70,4 @@
mem_side = MasterPort("Port on side closer to MEM")
addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for
the CPU-side port")
system = Param.System(Parent.any, "System we belong to")
+ tags = Param.BaseTags(LRU(), "Tag Store for LRU caches")
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/base.cc Thu Jun 27 05:49:50 2013 -0400
@@ -773,13 +773,19 @@
BaseCache *
BaseCacheParams::create()
{
- int numSets = size / (assoc * block_size);
+ unsigned numSets = size / (assoc * block_size);
- if (numSets == 1) {
- FALRU *tags = new FALRU(block_size, size, hit_latency);
- return new Cache<FALRU>(this, tags);
+ assert(tags);
+
+ if (dynamic_cast<FALRU*>(tags)) {
+ if (numSets != 1)
+ fatal("Got FALRU tags with more than one set\n");
+ return new Cache<FALRU>(this);
+ } else if (dynamic_cast<LRU*>(tags)) {
+ if (numSets == 1)
+ warn("Consider using FALRU tags for a fully associative cache\n");
+ return new Cache<LRU>(this);
} else {
- LRU *tags = new LRU(numSets, block_size, assoc, hit_latency);
- return new Cache<LRU>(this, tags);
+ fatal("No suitable tags selected\n");
}
}
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/cache.hh Thu Jun 27 05:49:50 2013 -0400
@@ -409,7 +409,7 @@
public:
/** Instantiates a basic cache object. */
- Cache(const Params *p, TagStore *tags);
+ Cache(const Params *p);
void regStats();
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/cache_impl.hh Thu Jun 27 05:49:50 2013 -0400
@@ -63,9 +63,9 @@
#include "sim/sim_exit.hh"
template<class TagStore>
-Cache<TagStore>::Cache(const Params *p, TagStore *tags)
+Cache<TagStore>::Cache(const Params *p)
: BaseCache(p),
- tags(tags),
+ tags(dynamic_cast<TagStore*>(p->tags)),
prefetcher(p->prefetcher),
doFastWrites(true),
prefetchOnAccess(p->prefetch_on_access)
@@ -88,7 +88,6 @@
Cache<TagStore>::regStats()
{
BaseCache::regStats();
- tags->regStats(name());
}
template<class TagStore>
@@ -322,8 +321,7 @@
incMissCount(pkt);
return false;
}
- int master_id = pkt->req->masterId();
- tags->insertBlock(pkt->getAddr(), blk, master_id);
+ tags->insertBlock(pkt, blk);
blk->status = BlkValid | BlkReadable;
}
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
@@ -1219,8 +1217,7 @@
tempBlock->tag = tags->extractTag(addr);
DPRINTF(Cache, "using temp block for %x\n", addr);
} else {
- int id = pkt->req->masterId();
- tags->insertBlock(pkt->getAddr(), blk, id);
+ tags->insertBlock(pkt, blk);
}
// we should never be overwriting a valid block
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/tags/SConscript
--- a/src/mem/cache/tags/SConscript Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/tags/SConscript Thu Jun 27 05:49:50 2013 -0400
@@ -33,7 +33,8 @@
if env['TARGET_ISA'] == 'no':
Return()
+SimObject('Tags.py')
+
Source('base.cc')
Source('fa_lru.cc')
Source('lru.cc')
-Source('cacheset.cc')
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/tags/Tags.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/cache/tags/Tags.py Thu Jun 27 05:49:50 2013 -0400
@@ -0,0 +1,65 @@
+# Copyright (c) 2012-2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Prakash Ramrakhyani
+
+from m5.params import *
+from m5.proxy import *
+from ClockedObject import ClockedObject
+
+class BaseTags(ClockedObject):
+ type = 'BaseTags'
+ abstract = True
+ cxx_header = "mem/cache/tags/base.hh"
+ # Get the size from the parent (cache)
+ size = Param.MemorySize(Parent.size, "capacity in bytes")
+
+ # Get the block size from the parent (cache)
+ block_size = Param.Int(Parent.block_size, "block size in bytes")
+
+ # Get the hit latency from the parent (cache)
+ hit_latency = Param.Cycles(Parent.hit_latency,
+ "The hit latency for this cache")
+
+class LRU(BaseTags):
+ type = 'LRU'
+ cxx_class = 'LRU'
+ cxx_header = "mem/cache/tags/lru.hh"
+ assoc = Param.Int(Parent.assoc, "associativity")
+
+class FALRU(BaseTags):
+ type = 'FALRU'
+ cxx_class = 'FALRU'
+ cxx_header = "mem/cache/tags/fa_lru.hh"
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/tags/base.cc
--- a/src/mem/cache/tags/base.cc Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/tags/base.cc Thu Jun 27 05:49:50 2013 -0400
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -41,54 +53,59 @@
using namespace std;
+BaseTags::BaseTags(const Params *p)
+ : ClockedObject(p), blkSize(p->block_size), size(p->size),
+ hitLatency(p->hit_latency)
+{
+}
+
void
BaseTags::setCache(BaseCache *_cache)
{
cache = _cache;
- objName = cache->name();
}
void
-BaseTags::regStats(const string &name)
+BaseTags::regStats()
{
using namespace Stats;
replacements
.init(maxThreadsPerCPU)
- .name(name + ".replacements")
+ .name(name() + ".replacements")
.desc("number of replacements")
.flags(total)
;
tagsInUse
- .name(name + ".tagsinuse")
+ .name(name() + ".tagsinuse")
.desc("Cycle average of tags in use")
;
totalRefs
- .name(name + ".total_refs")
+ .name(name() + ".total_refs")
.desc("Total number of references to valid blocks.")
;
sampledRefs
- .name(name + ".sampled_refs")
+ .name(name() + ".sampled_refs")
.desc("Sample count of references to valid blocks.")
;
avgRefs
- .name(name + ".avg_refs")
+ .name(name() + ".avg_refs")
.desc("Average number of references to valid blocks.")
;
avgRefs = totalRefs/sampledRefs;
warmupCycle
- .name(name + ".warmup_cycle")
+ .name(name() + ".warmup_cycle")
.desc("Cycle when the warmup percentage was hit.")
;
occupancies
.init(cache->system->maxMasters())
- .name(name + ".occ_blocks")
+ .name(name() + ".occ_blocks")
.desc("Average occupied blocks per requestor")
.flags(nozero | nonan)
;
@@ -97,7 +114,7 @@
}
avgOccs
- .name(name + ".occ_percent")
+ .name(name() + ".occ_percent")
.desc("Average percentage of cache occupancy")
.flags(nozero | total)
;
diff -r a31d1a0888a2 -r 485399270ca1 src/mem/cache/tags/base.hh
--- a/src/mem/cache/tags/base.hh Thu Jun 27 05:49:50 2013 -0400
+++ b/src/mem/cache/tags/base.hh Thu Jun 27 05:49:50 2013 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -53,21 +53,27 @@
#include "base/callback.hh"
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