changeset eec242a5252d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=eec242a5252d
description:
        regressions: update a couple of configs
        The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been
        updated correctly in the patch 6e6cefc1db1f.

diffstat:

 tests/configs/pc-simple-timing-ruby.py |  7 +++++--
 tests/configs/t1000-simple-atomic.py   |  4 +++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diffs (34 lines):

diff -r 04414c223a6a -r eec242a5252d tests/configs/pc-simple-timing-ruby.py
--- a/tests/configs/pc-simple-timing-ruby.py    Fri Jun 28 21:42:27 2013 -0500
+++ b/tests/configs/pc-simple-timing-ruby.py    Tue Jul 02 10:10:58 2013 -0500
@@ -56,10 +56,13 @@
 #the system
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
-                                     mdesc=mdesc, Ruby=True,
+                                     mdesc=mdesc, Ruby=True)
 
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
-system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
+system.clk_domain = SrcClockDomain(clock = '1GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
+              for i in xrange(options.num_cpus)]
 
 Ruby.create_system(options, system, system.piobus, system._dma_ports)
 
diff -r 04414c223a6a -r eec242a5252d tests/configs/t1000-simple-atomic.py
--- a/tests/configs/t1000-simple-atomic.py      Fri Jun 28 21:42:27 2013 -0500
+++ b/tests/configs/t1000-simple-atomic.py      Tue Jul 02 10:10:58 2013 -0500
@@ -31,8 +31,10 @@
 m5.util.addToPath('../configs/common')
 import FSConfig
 
-cpu = AtomicSimpleCPU(cpu_id=0)
 system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
+system.clk_domain = SrcClockDomain(clock = '1GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
+cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
 system.cpu = cpu
 # create the interrupt controller
 cpu.createInterruptController()
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