Hi,
I'm hacking some changes into src/mem/bridge so that subordinate
peripherals are reachable by the CPU without manual configuration of
range lists, especially when in a hierarchy of buses. Ali tells me that
there used to be this or similar functionality, but it got taken out for
some reason he didn't remember. (Andreas?) It'd be great to get some
background on that if possible.
At least in the x86 case, there is a cycle between membus and iobus (so
that PCI agents can initiate DMA transactions), so the approach I'm
going to take is to compare the subordinate bus's range list with the
superordinate bus, and forward only those addresses that don't exist on
the superordinate bus.
In order to do this, I need to get a reference to the upstream bridge's
SlavePort into the downstream bridge. I can see how a class like Bridge
instantiates other classes (like SlavePort or, rather, BridgeSlavePort),
and I see how to pass simple parameters into a C++ class from its Python
equivalent, but I don't see how to pass a reference to another C++ class.
I would imagine that a mechanism similar to the port connection might do
the job, but I don't quite see how that works, either. Apologies, I'm
an FPGA guy and it's been years since I did anything serious in C++.
Any pointers (so to say) would be most welcome.
Thanks,
David.
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