changeset 7ad2b0186a32 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7ad2b0186a32
description:
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.
Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.
A follow-on patch updates the configuration scripts accordingly.
diffstat:
src/arch/arm/isa.cc | 4 +-
src/cpu/base.cc | 2 +-
src/cpu/base.hh | 10 ++++++-
src/cpu/base_dyn_inst.hh | 4 +-
src/cpu/checker/cpu.cc | 8 ++---
src/cpu/inorder/resources/cache_unit.cc | 2 +-
src/cpu/o3/fetch.hh | 5 +---
src/cpu/o3/fetch_impl.hh | 40 +++++++----------------------
src/cpu/o3/lsq_unit_impl.hh | 13 +--------
src/cpu/simple/atomic.cc | 8 +----
src/cpu/simple/timing.cc | 4 +-
src/cpu/testers/memtest/memtest.cc | 11 +++----
src/cpu/testers/traffic_gen/traffic_gen.cc | 7 ++---
src/cpu/thread_state.cc | 3 +-
src/dev/dma_device.cc | 2 +-
src/dev/dma_device.hh | 6 ++--
src/mem/Bus.py | 2 -
src/mem/SimpleDRAM.py | 2 +-
src/mem/addr_mapper.cc | 18 -------------
src/mem/addr_mapper.hh | 14 ----------
src/mem/bridge.cc | 5 ---
src/mem/bus.cc | 32 +-----------------------
src/mem/bus.hh | 11 --------
src/mem/cache/BaseCache.py | 1 -
src/mem/cache/base.cc | 4 +-
src/mem/cache/cache.hh | 6 ----
src/mem/cache/tags/Tags.py | 4 +-
src/mem/coherent_bus.hh | 12 ---------
src/mem/comm_monitor.cc | 12 ---------
src/mem/comm_monitor.hh | 14 ----------
src/mem/fs_translating_port_proxy.cc | 11 +++++---
src/mem/fs_translating_port_proxy.hh | 2 +-
src/mem/noncoherent_bus.hh | 12 ---------
src/mem/port.cc | 12 ---------
src/mem/port.hh | 22 ----------------
src/mem/port_proxy.cc | 2 +-
src/mem/port_proxy.hh | 8 ++++-
src/mem/ruby/system/RubyPort.cc | 6 ----
src/mem/ruby/system/RubyPort.hh | 1 -
src/mem/se_translating_port_proxy.cc | 5 ++-
src/mem/simple_dram.cc | 3 +-
src/sim/System.py | 2 +
src/sim/system.cc | 12 ++++++--
src/sim/system.hh | 8 ++++++
44 files changed, 94 insertions(+), 278 deletions(-)
diffs (truncated from 1115 to 300 lines):
diff -r bba03800b376 -r 7ad2b0186a32 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Thu Jul 18 08:29:47 2013 -0400
+++ b/src/arch/arm/isa.cc Thu Jul 18 08:31:16 2013 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -238,7 +238,7 @@
//all caches have the same line size in gem5
//4 byte words in ARM
unsigned lineSizeWords =
- tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
+ tc->getSystemPtr()->cacheLineSize() / 4;
unsigned log2LineSizeWords = 0;
while (lineSizeWords >>= 1) {
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/base.cc
--- a/src/cpu/base.cc Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/base.cc Thu Jul 18 08:31:16 2013 -0400
@@ -119,7 +119,7 @@
_instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
- _switchedOut(p->switched_out),
+ _switchedOut(p->switched_out),
_cacheLineSize(p->system->cacheLineSize()),
interrupts(p->interrupts), profileEvent(NULL),
numThreads(p->numThreads), system(p->system)
{
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/base.hh
--- a/src/cpu/base.hh Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/base.hh Thu Jul 18 08:31:16 2013 -0400
@@ -57,12 +57,12 @@
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/insttracer.hh"
+#include "sim/system.hh"
struct BaseCPUParams;
class BranchPred;
class CheckerCPU;
class ThreadContext;
-class System;
class CPUProgressEvent : public Event
{
@@ -117,6 +117,9 @@
/** Is the CPU switched out or active? */
bool _switchedOut;
+ /** Cache the cache line size that we get from the system */
+ const unsigned int _cacheLineSize;
+
public:
/**
@@ -343,6 +346,11 @@
System *system;
/**
+ * Get the cache line size of the system.
+ */
+ inline unsigned int cacheLineSize() const { return _cacheLineSize; }
+
+ /**
* Serialize this object to the given output stream.
*
* @note CPU models should normally overload the serializeThread()
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/base_dyn_inst.hh Thu Jul 18 08:31:16 2013 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011,2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -976,7 +976,7 @@
RequestPtr &sreqHigh)
{
// Check to see if the request crosses the next level block boundary.
- unsigned block_size = cpu->getDataPort().peerBlockSize();
+ unsigned block_size = cpu->cacheLineSize();
Addr addr = req->getVaddr();
Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/checker/cpu.cc Thu Jul 18 08:31:16 2013 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011,2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -142,9 +142,8 @@
CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
{
Fault fault = NoFault;
- unsigned blockSize = dcachePort->peerBlockSize();
int fullSize = size;
- Addr secondAddr = roundDown(addr + size - 1, blockSize);
+ Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
bool checked_flags = false;
bool flags_match = true;
Addr pAddr = 0x0;
@@ -236,10 +235,9 @@
bool flags_match = true;
Addr pAddr = 0x0;
- unsigned blockSize = dcachePort->peerBlockSize();
int fullSize = size;
- Addr secondAddr = roundDown(addr + size - 1, blockSize);
+ Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
if (secondAddr > addr)
size = secondAddr - addr;
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Thu Jul 18 08:31:16 2013 -0400
@@ -112,7 +112,7 @@
reqs[i] = new CacheRequest(this);
}
- cacheBlkSize = cachePort->peerBlockSize();
+ cacheBlkSize = cpu->cacheLineSize();
cacheBlkMask = cacheBlkSize - 1;
initSlots();
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/o3/fetch.hh Thu Jul 18 08:31:16 2013 -0400
@@ -216,9 +216,6 @@
/** Initialize stage. */
void startupStage();
- /** Tells the fetch stage that the Icache is set. */
- void setIcache();
-
/** Handles retrying the fetch access. */
void recvRetry();
@@ -464,7 +461,7 @@
ThreadID retryTid;
/** Cache block size. */
- int cacheBlkSize;
+ unsigned int cacheBlkSize;
/** Mask to get a cache block's address. */
Addr cacheBlkMask;
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/o3/fetch_impl.hh Thu Jul 18 08:31:16 2013 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -81,6 +81,8 @@
fetchWidth(params->fetchWidth),
retryPkt(NULL),
retryTid(InvalidThreadID),
+ cacheBlkSize(cpu->cacheLineSize()),
+ cacheBlkMask(cacheBlkSize - 1),
numThreads(params->numThreads),
numFetchingThreads(params->smtNumFetchingThreads),
finishTranslationEvent(this)
@@ -126,11 +128,17 @@
instSize = sizeof(TheISA::MachInst);
for (int i = 0; i < Impl::MaxThreads; i++) {
- cacheData[i] = NULL;
decoder[i] = new TheISA::Decoder;
}
branchPred = params->branchPred;
+
+ for (ThreadID tid = 0; tid < numThreads; tid++) {
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+ }
}
template <class Impl>
@@ -336,34 +344,6 @@
wroteToTimeBuffer = false;
_status = Inactive;
-
- // this CPU could still be unconnected if we are restoring from a
- // checkpoint and this CPU is to be switched in, thus we can only
- // do this here if the instruction port is actually connected, if
- // not we have to do it as part of takeOverFrom.
- if (cpu->getInstPort().isConnected())
- setIcache();
-}
-
-template<class Impl>
-void
-DefaultFetch<Impl>::setIcache()
-{
- assert(cpu->getInstPort().isConnected());
-
- // Size of cache block.
- cacheBlkSize = cpu->getInstPort().peerBlockSize();
-
- // Create mask to get rid of offset bits.
- cacheBlkMask = (cacheBlkSize - 1);
-
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- // Create space to store a cache line.
- if (!cacheData[tid])
- cacheData[tid] = new uint8_t[cacheBlkSize];
- cacheDataPC[tid] = 0;
- cacheDataValid[tid] = false;
- }
}
template<class Impl>
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/o3/lsq_unit_impl.hh Thu Jul 18 08:31:16 2013 -0400
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2010-2012 ARM Limited
* All rights reserved
@@ -190,7 +191,7 @@
isLoadBlocked = false;
loadBlockedHandled = false;
- cacheBlockMask = 0;
+ cacheBlockMask = ~(cpu->cacheLineSize() - 1);
}
template<class Impl>
@@ -419,16 +420,6 @@
{
int load_idx = loadHead;
- if (!cacheBlockMask) {
- assert(dcachePort);
- Addr bs = dcachePort->peerBlockSize();
-
- // Make sure we actually got a size
- assert(bs != 0);
-
- cacheBlockMask = ~(bs - 1);
- }
-
// Unlock the cpu-local monitor when the CPU sees a snoop to a locked
// address. The CPU can speculatively execute a LL operation after a
pending
// SC operation in the pipeline and that can make the cache monitor the CPU
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Thu Jul 18 08:29:47 2013 -0400
+++ b/src/cpu/simple/atomic.cc Thu Jul 18 08:31:16 2013 -0400
@@ -287,14 +287,12 @@
traceData->setAddr(addr);
}
- //The block size of our peer.
- unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
int fullSize = size;
//The address of the second part of this access if it needs to be split
//across a cache line boundary.
- Addr secondAddr = roundDown(addr + size - 1, blockSize);
+ Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
if (secondAddr > addr)
size = secondAddr - addr;
@@ -375,14 +373,12 @@
traceData->setAddr(addr);
}
- //The block size of our peer.
- unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
int fullSize = size;
//The address of the second part of this access if it needs to be split
//across a cache line boundary.
- Addr secondAddr = roundDown(addr + size - 1, blockSize);
+ Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
if(secondAddr > addr)
size = secondAddr - addr;
diff -r bba03800b376 -r 7ad2b0186a32 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Thu Jul 18 08:29:47 2013 -0400
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