----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1809/#review4536 -----------------------------------------------------------
Some minor concerns that hopefully can be fixed quickly. Thanks for the update. configs/common/CacheConfig.py <http://reviews.gem5.org/r/1809/#comment4249> Stick to "a=b" or "a = b" throughout. This applies to the I and D cache as well. configs/common/Options.py <http://reviews.gem5.org/r/1809/#comment4250> I'm tempted to say we group these based on L1, L2 and L3. Any other opinions on this one? src/mem/cache/BaseCache.py <http://reviews.gem5.org/r/1809/#comment4251> I think we might have touched on this already, but I'm all in favour of changing this to read_latency as part of this patch. src/mem/cache/BaseCache.py <http://reviews.gem5.org/r/1809/#comment4252> Is there a point in having these defaults if the command-line options override then anyways? Int -> Unsigned? src/mem/cache/BaseCache.py <http://reviews.gem5.org/r/1809/#comment4253> Unsigned src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4254> A line or two per method (in doxygen format) would be greatly appreciated. src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4255> I'd say do the rename as part of this patch. Anyone else got opinions on this one? src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4256> Already do this once in the constructor. src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4257> I would suggest to precompute the mask and shift in the constructor as I imagine this will be called a lot. Any idea what this patch does to the simulator performance btw? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4258> should officially be bank_id (as it is a local variable) src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4259> This is fine, just wanted to point out that you can also do: for (auto b = cache->bank.begin(); b != cache->bank.end(); ++b) if ((*b)->serviceDone()) etc The unfortunate bit here is that we iterate over all the banks for every cache access. I don't know what the performance impact is, but it worries me a bit. The benefit of having events per bank is that they only do what they have to, and only when they have to. src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4260> if (blocked) ? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4261> 80 char src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4262> Same concern as above. I'd suggest to add an event per bank to do the clearing. - Andreas Hansson On July 18, 2013, 7:33 p.m., Xiangyu Dong wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1809/ > ----------------------------------------------------------- > > (Updated July 18, 2013, 7:33 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9817:fc242bb34728 > --------------------------- > mem: model data array bank in classic cache > The classic cache does not model data array bank, i.e. if a read/write is > being > serviced by a cache bank, no other requests should be sent to this bank. > This patch models a multi-bank cache. Features include: > 1. detect if the bank interleave granularity is larger than cache line size > 2. add CacheBank debug flag > 3. Differentiate read and write latency > 3a. read latency is still named as hit_latency > 3b. write latency is named as write_latency > 4. Add write_latency, num_banks, bank_itlv_bit into the Python parser > Not modeled in this patch: > Due to the lack of retry mechanism in the cache master port, the access form > the memory side will not be denied if the bank is in service. Instead, the > bank > service time will be extended. This is equivalent to an infinite write buffer > for cache fill operations. > > > Diffs > ----- > > configs/common/CacheConfig.py 3b3b94536547 > configs/common/Caches.py 3b3b94536547 > configs/common/Options.py 3b3b94536547 > src/mem/cache/BaseCache.py 3b3b94536547 > src/mem/cache/SConscript 3b3b94536547 > src/mem/cache/base.hh 3b3b94536547 > src/mem/cache/base.cc 3b3b94536547 > src/mem/cache/cache_impl.hh 3b3b94536547 > > Diff: http://reviews.gem5.org/r/1809/diff/ > > > Testing > ------- > > > Thanks, > > Xiangyu Dong > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
