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Almost there :-) Do all the normal regressions pass (with the 1 bank default)? If so, do you know what the performance impact is? configs/common/Caches.py <http://reviews.gem5.org/r/1809/#comment4298> Could we not let num_banks be 1 by default and leave this out here? Similary so for the interleaving bit. Make it 0 by default and if num_banks is 1 then it is never needed. configs/common/Options.py <http://reviews.gem5.org/r/1809/#comment4299> Could you add "(cycles)" at the end? configs/common/Options.py <http://reviews.gem5.org/r/1809/#comment4300> I am not sure it's worth removing this functionality, but would we ever want to interleave on anything besides cache line granularity? src/mem/cache/BaseCache.py <http://reviews.gem5.org/r/1809/#comment4301> See previous remark. I suggest making this 1 by default src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4302> perhaps add a sentence that this is to model contention and does not actually hold any data src/mem/cache/base.hh <http://reviews.gem5.org/r/1809/#comment4303> port -> bank src/mem/cache/base.cc <http://reviews.gem5.org/r/1809/#comment4304> I would suggest p->bank_intlv_high_bit ? p->bank_intlv_high_bit : ceilLog2(blkSize) + bankIntlvBits src/mem/cache/base.cc <http://reviews.gem5.org/r/1809/#comment4305> The name is a bit misleading, is it not? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4306> else? fatal? lat = readLatency? I would think if pkt->isWrite(), lat = writeLatency, and in all other cases lat = readLatency. src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4307> Do outside the if/else? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4308> I would really consider this a todo and a next follow-on patch src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4309> bank_busy? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4310> ..., wait until the cache is unblocked and then send a retry src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1809/#comment4311> Could it be extended? - Andreas Hansson On July 31, 2013, 9:52 p.m., Xiangyu Dong wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1809/ > ----------------------------------------------------------- > > (Updated July 31, 2013, 9:52 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9818:d6c890fd0eab > --------------------------- > mem: model data array bank in classic cache > The classic cache does not model data array bank, i.e. if a read/write is > being > serviced by a cache bank, no other requests should be sent to this bank. > This patch models a multi-bank cache. Features include: > 1. detect if the bank interleave granularity is larger than cache line size > 2. add CacheBank debug flag > 3. Differentiate read and write latency > 3a. read latency is still named as hit_latency > 3b. write latency is named as write_latency > 4. Add write_latency, num_banks, bank_itlv_bit into the Python parser > Not modeled in this patch: > Due to the lack of retry mechanism in the cache master port, the access form > the memory side will not be denied if the bank is in service. Instead, the > bank > service time will be extended. This is equivalent to an infinite write buffer > for cache fill operations. > > > Diffs > ----- > > configs/common/CacheConfig.py 2492d7ccda7e > configs/common/Caches.py 2492d7ccda7e > configs/common/O3_ARM_v7a.py 2492d7ccda7e > configs/common/Options.py 2492d7ccda7e > src/mem/cache/BaseCache.py 2492d7ccda7e > src/mem/cache/SConscript 2492d7ccda7e > src/mem/cache/base.hh 2492d7ccda7e > src/mem/cache/base.cc 2492d7ccda7e > src/mem/cache/cache_impl.hh 2492d7ccda7e > src/mem/cache/tags/Tags.py 2492d7ccda7e > > Diff: http://reviews.gem5.org/r/1809/diff/ > > > Testing > ------- > > > Thanks, > > Xiangyu Dong > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
