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Ship it! LTGM! Thanks! - Ali Saidi On Aug. 13, 2013, 9:15 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1726/ > ----------------------------------------------------------- > > (Updated Aug. 13, 2013, 9:15 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9821:9e2898b0e9bd > --------------------------- > cpu: allow the fetch buffer to be smaller than a cache line > > the current implementation of the fetch buffer in the o3 cpu > is only allowed to be the size of a cache line. some > architectures, e.g., ARM, have fetch buffers smaller than a cache > line, see slide 22 at: > http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf > > this patch allows the fetch buffer to be set to values smaller > than a cache line. > > > Diffs > ----- > > configs/common/O3_ARM_v7a.py 2f9aecba23623a188e3c775530cdc47dc78dec6e > src/SConscript 2f9aecba23623a188e3c775530cdc47dc78dec6e > src/cpu/o3/O3CPU.py 2f9aecba23623a188e3c775530cdc47dc78dec6e > src/cpu/o3/fetch.hh 2f9aecba23623a188e3c775530cdc47dc78dec6e > src/cpu/o3/fetch_impl.hh 2f9aecba23623a188e3c775530cdc47dc78dec6e > > Diff: http://reviews.gem5.org/r/1726/diff/ > > > Testing > ------- > > ran several of the shorter SPEC CPU2006 benchmarks with test input. > icache.overall_accesses::total stat was validated against real > cortex A15 hardware, the value is much closer now. > > regressions pass > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
