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Review request for Default. Repository: gem5 Description ------- Allow forcing tagged prefetches for IFETCH requests given to stride prefetchers. For systems with a tightly coupled L2, a stride-based prefetcher may observe access requests from both instruction and data L1 caches. However, the PC address of an instruction miss gives no relevant training information to the stride based prefetcher(there is no stride to train). In theses cases, its better if the L2 stride prefetcher simply reverted back to a simple N-block ahead prefetcher. This patch enables this option. Note: This patch relies upon the earlier patch submitted in review request #2000. Negligibly improves performance on SPEC, but SPEC isn't an instruction footprint heavy suite. Diffs ----- src/mem/cache/prefetch/Prefetcher.py a317086a3e19 src/mem/cache/prefetch/stride.hh a317086a3e19037a2b0c8332b7cb8c411aab390d src/mem/cache/prefetch/stride.cc a317086a3e19 Diff: http://reviews.gem5.org/r/2001/diff/ Testing ------- Thanks, Mitch Hayenga _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
