changeset 69bb50791e25 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=69bb50791e25
description:
        ruby: converts sparse memory stats to gem5 style

diffstat:

 src/mem/ruby/slicc_interface/AbstractController.hh |   1 -
 src/mem/ruby/system/DirectoryMemory.cc             |   4 +-
 src/mem/ruby/system/DirectoryMemory.hh             |   2 +-
 src/mem/ruby/system/SparseMemory.cc                |  42 +++++++--------------
 src/mem/ruby/system/SparseMemory.hh                |  17 +++-----
 src/mem/ruby/system/System.cc                      |   9 ----
 src/mem/slicc/symbols/StateMachine.py              |  17 --------
 7 files changed, 25 insertions(+), 67 deletions(-)

diffs (202 lines):

diff -r a317086a3e19 -r 69bb50791e25 
src/mem/ruby/slicc_interface/AbstractController.hh
--- a/src/mem/ruby/slicc_interface/AbstractController.hh        Thu Sep 05 
13:53:54 2013 -0400
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh        Fri Sep 06 
16:21:28 2013 -0500
@@ -71,7 +71,6 @@
     virtual DataBlock& getDataBlock(const Address& addr) = 0;
 
     virtual void print(std::ostream & out) const = 0;
-    virtual void printStats(std::ostream & out) const = 0;
     virtual void wakeup() = 0;
     virtual void clearStats() = 0;
     virtual void regStats() = 0;
diff -r a317086a3e19 -r 69bb50791e25 src/mem/ruby/system/DirectoryMemory.cc
--- a/src/mem/ruby/system/DirectoryMemory.cc    Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/ruby/system/DirectoryMemory.cc    Fri Sep 06 16:21:28 2013 -0500
@@ -192,10 +192,10 @@
 }
 
 void
-DirectoryMemory::printStats(ostream& out) const
+DirectoryMemory::regStats()
 {
     if (m_use_map) {
-        m_sparseMemory->printStats(out);
+        m_sparseMemory->regStats(name());
     }
 }
 
diff -r a317086a3e19 -r 69bb50791e25 src/mem/ruby/system/DirectoryMemory.hh
--- a/src/mem/ruby/system/DirectoryMemory.hh    Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/ruby/system/DirectoryMemory.hh    Fri Sep 06 16:21:28 2013 -0500
@@ -63,7 +63,7 @@
     void invalidateBlock(PhysAddress address);
 
     void print(std::ostream& out) const;
-    void printStats(std::ostream& out) const;
+    void regStats();
 
     void recordRequestType(DirectoryRequestType requestType);
 
diff -r a317086a3e19 -r 69bb50791e25 src/mem/ruby/system/SparseMemory.cc
--- a/src/mem/ruby/system/SparseMemory.cc       Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/ruby/system/SparseMemory.cc       Fri Sep 06 16:21:28 2013 -0500
@@ -57,15 +57,6 @@
             m_number_of_bits_per_level[level] = even_level_bits;
     }
     m_map_head = new SparseMapType;
-
-    m_total_adds = 0;
-    m_total_removes = 0;
-    m_adds_per_level = new uint64_t[m_number_of_levels];
-    m_removes_per_level = new uint64_t[m_number_of_levels];
-    for (int level = 0; level < m_number_of_levels; level++) {
-        m_adds_per_level[level] = 0;
-        m_removes_per_level[level] = 0;
-    }
 }
 
 SparseMemory::~SparseMemory()
@@ -73,8 +64,6 @@
     recursivelyRemoveTables(m_map_head, 0);
     delete m_map_head;
     delete [] m_number_of_bits_per_level;
-    delete [] m_adds_per_level;
-    delete [] m_removes_per_level;
 }
 
 // Recursively search table hierarchy for the lowest level table.
@@ -409,21 +398,20 @@
 }
 
 void
-SparseMemory::print(ostream& out) const
+SparseMemory::regStats(const string &name)
 {
+    m_total_adds.name(name + ".total_adds");
+
+    m_adds_per_level
+        .init(m_number_of_levels)
+        .name(name + ".adds_per_level")
+        .flags(Stats::pdf | Stats::total)
+        ;
+
+    m_total_removes.name(name + ".total_removes");
+    m_removes_per_level
+        .init(m_number_of_levels)
+        .name(name + ".removes_per_level")
+        .flags(Stats::pdf | Stats::total)
+        ;
 }
-
-void
-SparseMemory::printStats(ostream& out) const
-{
-    out << "total_adds: " << m_total_adds << " [";
-    for (int level = 0; level < m_number_of_levels; level++) {
-        out << m_adds_per_level[level] << " ";
-    }
-    out << "]" << endl;
-    out << "total_removes: " << m_total_removes << " [";
-    for (int level = 0; level < m_number_of_levels; level++) {
-        out << m_removes_per_level[level] << " ";
-    }
-    out << "]" << endl;
-}
diff -r a317086a3e19 -r 69bb50791e25 src/mem/ruby/system/SparseMemory.hh
--- a/src/mem/ruby/system/SparseMemory.hh       Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/ruby/system/SparseMemory.hh       Fri Sep 06 16:21:28 2013 -0500
@@ -31,8 +31,10 @@
 #define __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__
 
 #include <iostream>
+#include <string>
 
 #include "base/hashmap.hh"
+#include "base/statistics.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractEntry.hh"
@@ -67,14 +69,9 @@
     void recordBlocks(int cntrl_id, CacheRecorder *) const;
 
     AbstractEntry* lookup(const Address& address);
-
-    // Print cache contents
-    void print(std::ostream& out) const;
-    void printStats(std::ostream& out) const;
+    void regStats(const std::string &name);
 
   private:
-    // Private Methods
-
     // Private copy constructor and assignment operator
     SparseMemory(const SparseMemory& obj);
     SparseMemory& operator=(const SparseMemory& obj);
@@ -92,10 +89,10 @@
     int m_number_of_levels;
     int* m_number_of_bits_per_level;
 
-    uint64_t m_total_adds;
-    uint64_t m_total_removes;
-    uint64_t* m_adds_per_level;
-    uint64_t* m_removes_per_level;
+    Stats::Scalar m_total_adds;
+    Stats::Vector m_adds_per_level;
+    Stats::Scalar m_total_removes;
+    Stats::Vector m_removes_per_level;
 };
 
 #endif // __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__
diff -r a317086a3e19 -r 69bb50791e25 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc     Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/ruby/system/System.cc     Fri Sep 06 16:21:28 2013 -0500
@@ -145,15 +145,6 @@
 
     m_profiler_ptr->printStats(out);
     m_network_ptr->printStats(out);
-
-    for (uint32_t i = 0;i < g_abs_controls.size(); ++i) {
-        for (map<uint32_t, AbstractController *>::iterator it =
-                g_abs_controls[i].begin();
-             it != g_abs_controls[i].end(); ++it) {
-
-            ((*it).second)->printStats(out);
-        }
-    }
 }
 
 void
diff -r a317086a3e19 -r 69bb50791e25 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py     Thu Sep 05 13:53:54 2013 -0400
+++ b/src/mem/slicc/symbols/StateMachine.py     Fri Sep 06 16:21:28 2013 -0500
@@ -257,7 +257,6 @@
 
     void print(std::ostream& out) const;
     void wakeup();
-    void printStats(std::ostream& out) const;
     void clearStats();
     void regStats();
     void collateStats();
@@ -847,22 +846,6 @@
     out << "[$c_ident " << m_version << "]";
 }
 
-void
-$c_ident::printStats(ostream& out) const
-{
-''')
-        #
-        # Cache and Memory Controllers have specific profilers associated with
-        # them.  Print out these stats before dumping state transition stats.
-        #
-        for param in self.config_parameters:
-            if param.type_ast.type.ident == "DirectoryMemory":
-                assert(param.pointer)
-                code('    m_${{param.ident}}_ptr->printStats(out);')
-
-        code('''
-}
-
 void $c_ident::clearStats()
 {
     for (int state = 0; state < ${ident}_State_NUM; state++) {
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