Hey Andreas, I noticed that you've changed most of the occurrences of system.physmem over to system.mem_ctrls with these patches, but it looks like there are still some instances floating around. I think it's fine to leave the occurrences in the Ruby test config files, but I have a question about se.py: There, the classic memory model has shifted over to system.mem_ctrls, but the Ruby side is still using system.physmem. Since some of our derived patches rely on the same naming to find these memories, we'd like/need the names to be consistent for both full-system and SE mode with Ruby. Do you know of anything that is blocking the move to just using system.mem_ctrls in se.py for Ruby?
Thanks, Joel On Mon, Aug 19, 2013 at 2:46 AM, Andreas Hansson <[email protected]>wrote: > changeset 014ff1fbff6d in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=014ff1fbff6d > description: > config: Move the memory instantiation outside FSConfig > > This patch moves the instantiation of the memory controller outside > FSConfig and instead relies on the mem_ranges to pass the > information > to the caller (e.g. fs.py or one of the regression scripts). The > main > motivation for this change is to expose the structural composition > of > the memory system and allow more tuning and configuration without > adding a large number of options to the makeSystem functions. > > The patch updates the relevant example scripts to maintain the > current > functionality. As the order that ports are connected to the memory > bus > changes (in certain regresisons), some bus stats are shuffled > around. For example, what used to be layer 0 is now layer 1. > > Going forward, options will be added to support the addition of > multi-channel memory controllers. > > diffstat: > > configs/common/FSConfig.py | 69 > +++++++------------------- > configs/example/fs.py | 38 +++++++++----- > configs/example/ruby_fs.py | 13 +++- > configs/ruby/MESI_CMP_directory.py | 3 +- > configs/ruby/MI_example.py | 3 +- > configs/ruby/MOESI_CMP_directory.py | 3 +- > configs/ruby/MOESI_CMP_token.py | 3 +- > configs/ruby/MOESI_hammer.py | 3 +- > configs/ruby/Network_test.py | 3 +- > configs/ruby/Ruby.py | 3 +- > tests/configs/alpha_generic.py | 2 +- > tests/configs/arm_generic.py | 4 +- > tests/configs/base_config.py | 8 +++ > tests/configs/memtest-ruby.py | 2 + > tests/configs/pc-o3-timing.py | 1 + > tests/configs/pc-simple-atomic.py | 1 + > tests/configs/pc-simple-timing-ruby.py | 8 ++- > tests/configs/pc-simple-timing.py | 1 + > tests/configs/pc-switcheroo-full.py | 1 + > tests/configs/realview-o3-checker.py | 1 + > tests/configs/realview-o3-dual.py | 4 +- > tests/configs/realview-o3.py | 1 + > tests/configs/realview-simple-atomic-dual.py | 4 +- > tests/configs/realview-simple-atomic.py | 1 + > tests/configs/realview-simple-timing-dual.py | 4 +- > tests/configs/realview-simple-timing.py | 1 + > tests/configs/realview-switcheroo-atomic.py | 1 + > tests/configs/realview-switcheroo-full.py | 1 + > tests/configs/realview-switcheroo-o3.py | 1 + > tests/configs/realview-switcheroo-timing.py | 1 + > tests/configs/rubytest-ruby.py | 2 + > tests/configs/simple-timing-ruby.py | 2 + > tests/configs/t1000-simple-atomic.py | 10 +++- > tests/configs/tsunami-inorder.py | 1 + > tests/configs/tsunami-o3-dual.py | 4 +- > tests/configs/tsunami-o3.py | 1 + > tests/configs/tsunami-simple-atomic-dual.py | 4 +- > tests/configs/tsunami-simple-atomic.py | 1 + > tests/configs/tsunami-simple-timing-dual.py | 4 +- > tests/configs/tsunami-simple-timing.py | 1 + > tests/configs/tsunami-switcheroo-full.py | 1 + > tests/configs/twosys-tsunami-simple-atomic.py | 12 +++- > tests/configs/x86_generic.py | 1 - > 43 files changed, 137 insertions(+), 96 deletions(-) > > diffs (truncated from 818 to 300 lines): > > diff -r 410c4238a1bd -r 014ff1fbff6d configs/common/FSConfig.py > --- a/configs/common/FSConfig.py Mon Aug 19 03:52:26 2013 -0400 > +++ b/configs/common/FSConfig.py Mon Aug 19 03:52:27 2013 -0400 > @@ -55,7 +55,7 @@ > default = Self.badaddr_responder.pio > > > -def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None): > +def makeLinuxAlphaSystem(mem_mode, mdesc = None): > IO_address_space_base = 0x80000000000 > class BaseTsunami(Tsunami): > ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) > @@ -73,11 +73,9 @@ > # base address (including the PCI config space) > self.bridge = Bridge(delay='50ns', > ranges = [AddrRange(IO_address_space_base, > Addr.max)]) > - self.physmem = MemClass(range = AddrRange(mdesc.mem())) > - self.mem_ranges = [self.physmem.range] > + self.mem_ranges = [AddrRange(mdesc.mem())] > self.bridge.master = self.iobus.slave > self.bridge.slave = self.membus.master > - self.physmem.port = self.membus.master > self.disk0 = CowIdeDisk(driveID='master') > self.disk2 = CowIdeDisk(driveID='master') > self.disk0.childImage(mdesc.disk()) > @@ -104,15 +102,13 @@ > > return self > > -def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None): > +def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): > class BaseTsunami(Tsunami): > ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) > ide = IdeController(disks=[Parent.disk0, Parent.disk2], > pci_func=0, pci_dev=0, pci_bus=0) > - > - physmem = MemClass(range = AddrRange(mdesc.mem())) > - self = LinuxAlphaSystem(physmem = physmem) > - self.mem_ranges = [self.physmem.range] > + self = LinuxAlphaSystem() > + self.mem_ranges = [AddrRange(mdesc.mem())] > if not mdesc: > # generic system > mdesc = SysConfig() > @@ -121,13 +117,6 @@ > # Create pio bus to connect all device pio ports to rubymem's pio port > self.piobus = NoncoherentBus() > > - # > - # Pio functional accesses from devices need direct access to memory > - # RubyPort currently does support functional accesses. Therefore > provide > - # the piobus a direct connection to physical memory > - # > - self.piobus.master = physmem.port > - > self.disk0 = CowIdeDisk(driveID='master') > self.disk2 = CowIdeDisk(driveID='master') > self.disk0.childImage(mdesc.disk()) > @@ -157,7 +146,7 @@ > > return self > > -def makeSparcSystem(mem_mode, MemClass, mdesc = None): > +def makeSparcSystem(mem_mode, mdesc = None): > # Constants from iob.cc and uart8250.cc > iob_man_addr = 0x9800000000 > uart_pio_size = 8 > @@ -180,13 +169,10 @@ > self.t1000 = T1000() > self.t1000.attachOnChipIO(self.membus) > self.t1000.attachIO(self.iobus) > - self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB')) > - self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size > ='256MB')) > - self.mem_ranges = [self.physmem.range, self.physmem2.range] > + self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), > + AddrRange(Addr('2GB'), size ='256MB')] > self.bridge.master = self.iobus.slave > self.bridge.slave = self.membus.master > - self.physmem.port = self.membus.master > - self.physmem2.port = self.membus.master > self.rom.port = self.membus.master > self.nvram.port = self.membus.master > self.hypervisor_desc.port = self.membus.master > @@ -225,7 +211,7 @@ > > return self > > -def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None, > +def makeArmSystem(mem_mode, machine_type, mdesc = None, > dtb_filename = None, bare_metal=False): > assert machine_type > > @@ -273,8 +259,7 @@ > if bare_metal: > # EOT character on UART will end the simulation > self.realview.uart.end_on_eot = True > - self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem()))) > - self.mem_ranges = [self.physmem.range] > + self.mem_ranges = [AddrRange(mdesc.mem())] > else: > self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') > if dtb_filename is not None: > @@ -288,11 +273,8 @@ > > boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps > ' + \ > 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() > - > - self.physmem = MemClass(range = > AddrRange(self.realview.mem_start_addr, > - size = mdesc.mem()), > - conf_table_reported = True) > - self.mem_ranges = [self.physmem.range] > + self.mem_ranges = [AddrRange(self.realview.mem_start_addr, > + size = mdesc.mem())] > self.realview.setupBootLoader(self.membus, self, binary) > self.gic_cpu_addr = self.realview.gic.cpu_addr > self.flags_addr = self.realview.realview_io.pio_addr + 0x30 > @@ -300,8 +282,6 @@ > if mdesc.disk().lower().count('android'): > boot_flags += " init=/init " > self.boot_osflags = boot_flags > - > - self.physmem.port = self.membus.master > self.realview.attachOnChipIO(self.membus, self.bridge) > self.realview.attachIO(self.iobus) > self.intrctrl = IntrControl() > @@ -313,7 +293,7 @@ > return self > > > -def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None): > +def makeLinuxMipsSystem(mem_mode, mdesc = None): > class BaseMalta(Malta): > ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) > ide = IdeController(disks=[Parent.disk0, Parent.disk2], > @@ -327,11 +307,9 @@ > self.iobus = NoncoherentBus() > self.membus = MemBus() > self.bridge = Bridge(delay='50ns') > - self.physmem = MemClass(range = AddrRange('1GB')) > - self.mem_ranges = [self.physmem.range] > + self.mem_ranges = [AddrRange('1GB')] > self.bridge.master = self.iobus.slave > self.bridge.slave = self.membus.master > - self.physmem.port = self.membus.master > self.disk0 = CowIdeDisk(driveID='master') > self.disk2 = CowIdeDisk(driveID='master') > self.disk0.childImage(mdesc.disk()) > @@ -369,7 +347,6 @@ > APIC_range_size = 1 << 12; > > x86_sys.membus = MemBus() > - x86_sys.physmem.port = x86_sys.membus.master > > # North Bridge > x86_sys.iobus = NoncoherentBus() > @@ -409,19 +386,13 @@ > # North Bridge > x86_sys.piobus = NoncoherentBus() > > - # > - # Pio functional accesses from devices need direct access to memory > - # RubyPort currently does support functional accesses. Therefore > provide > - # the piobus a direct connection to physical memory > - # > - x86_sys.piobus.master = x86_sys.physmem.port > # add the ide to the list of dma devices that later need to attach to > # dma controllers > x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] > x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) > > > -def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = > None, > +def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, > Ruby = False): > if self == None: > self = X86System() > @@ -434,8 +405,7 @@ > self.mem_mode = mem_mode > > # Physical memory > - self.physmem = MemClass(range = AddrRange(mdesc.mem())) > - self.mem_ranges = [self.physmem.range] > + self.mem_ranges = [AddrRange(mdesc.mem())] > > # Platform > self.pc = Pc() > @@ -518,17 +488,16 @@ > self.intel_mp_table.base_entries = base_entries > self.intel_mp_table.ext_entries = ext_entries > > -def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, > +def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, > Ruby = False): > self = LinuxX86System() > > # Build up the x86 system and then specialize it for Linux > - makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby) > + makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) > > # We assume below that there's at least 1MB of memory. We'll require 2 > # just to avoid corner cases. > - phys_mem_size = sum(map(lambda mem: mem.range.size(), > - self.memories.unproxy(self))) > + phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) > assert(phys_mem_size >= 0x200000) > > self.e820_table.entries = \ > diff -r 410c4238a1bd -r 014ff1fbff6d configs/example/fs.py > --- a/configs/example/fs.py Mon Aug 19 03:52:26 2013 -0400 > +++ b/configs/example/fs.py Mon Aug 19 03:52:27 2013 -0400 > @@ -102,17 +102,16 @@ > np = options.num_cpus > > if buildEnv['TARGET_ISA'] == "alpha": > - test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0]) > + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) > elif buildEnv['TARGET_ISA'] == "mips": > - test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0]) > + test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) > elif buildEnv['TARGET_ISA'] == "sparc": > - test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0]) > + test_sys = makeSparcSystem(test_mem_mode, bm[0]) > elif buildEnv['TARGET_ISA'] == "x86": > - test_sys = makeLinuxX86System(test_mem_mode, TestMemClass, > - options.num_cpus, bm[0]) > + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) > elif buildEnv['TARGET_ISA'] == "arm": > - test_sys = makeArmSystem(test_mem_mode, options.machine_type, > - TestMemClass, bm[0], options.dtb_filename, > + test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], > + options.dtb_filename, > bare_metal=options.bare_metal) > else: > fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) > @@ -164,18 +163,24 @@ > > CacheConfig.config_cache(options, test_sys) > > +# Create the appropriate memory controllers and connect them to the > +# memory bus > +test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True) > + for r in test_sys.mem_ranges] > +for i in xrange(len(test_sys.mem_ctrls)): > + test_sys.mem_ctrls[i].port = test_sys.membus.master > + > if len(bm) == 2: > if buildEnv['TARGET_ISA'] == 'alpha': > - drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, > bm[1]) > + drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) > elif buildEnv['TARGET_ISA'] == 'mips': > - drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, > bm[1]) > + drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) > elif buildEnv['TARGET_ISA'] == 'sparc': > - drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1]) > + drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) > elif buildEnv['TARGET_ISA'] == 'x86': > - drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, > bm[1]) > + drive_sys = makeX86System(drive_mem_mode, np, bm[1]) > elif buildEnv['TARGET_ISA'] == 'arm': > - drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, > - DriveMemClass, bm[1]) > + drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, > bm[1]) > > # Create a source clock for the system and set the clock period > drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) > @@ -201,6 +206,13 @@ > drive_sys.iobridge.slave = drive_sys.iobus.master > drive_sys.iobridge.master = drive_sys.membus.slave > > + # Create the appropriate memory controllers and connect them to the > + # memory bus > + drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = > True) > + for r in drive_sys.mem_ranges] > + for i in xrange(len(drive_sys.mem_ctrls)): > + drive_sys.mem_ctrls[i].port = drive_sys.membus.master > + > drive_sys.init_param = options.init_param > root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) > elif len(bm) == 1: > diff -r 410c4238a1bd -r 014ff1fbff6d configs/example/ruby_fs.py > --- a/configs/example/ruby_fs.py Mon Aug 19 03:52:26 2013 -0400 > +++ b/configs/example/ruby_fs.py Mon Aug 19 03:52:27 2013 -0400 > @@ -83,10 +83,9 @@ > TestMemClass = Simulation.setMemClass(options) > > if buildEnv['TARGET_ISA'] == "alpha": > - system = makeLinuxAlphaRubySystem(test_mem_mode, TestMemClass, bm[0]) > + system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) > elif buildEnv['TARGET_ISA'] == "x86": > - system = makeLinuxX86System(test_mem_mode, TestMemClass, > - options.num_cpus, bm[0], True) > + system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], > True) > Simulation.setWorkCountOptions(system, options) > else: > fatal("incapable of building non-alpha or non-x86 full system!") > @@ -127,5 +126,13 @@ > > system.ruby._cpu_ruby_ports[i].access_phys_mem = True > > +# Create the appropriate memory controllers and connect them to the > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Wisconsin - Madison http://pages.cs.wisc.edu/~hestness/ _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
