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Ship it! Ship It! - Steve Reinhardt On Sept. 20, 2013, 6:19 a.m., Andreas Sandberg wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2024/ > ----------------------------------------------------------- > > (Updated Sept. 20, 2013, 6:19 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9885:f45348d9676b > --------------------------- > x86: Add support for m5ops through a memory mapped interface > > In order to support m5ops in virtualized environments, we need to use > a memory mapped interface. This changeset adds support for that by > reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR > interface for m5ops. The mapping is done in the > X86ISA::TLB::finalizePhysical() which means that it just works for all > of the CPU models, including virtualized ones. > > > Diffs > ----- > > configs/common/FSConfig.py 372d3611c693 > src/arch/x86/tlb.cc 372d3611c693 > util/m5/Makefile.x86 372d3611c693 > util/m5/m5.c 372d3611c693 > util/m5/m5op_x86.S 372d3611c693 > > Diff: http://reviews.gem5.org/r/2024/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Sandberg > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
