changeset 5924b77fb8fc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5924b77fb8fc
description:
        x86: Fix re-entrancy problems in x87 store instructions

        X87 store instructions typically loads and pops the top value of the
        stack and stores it in memory. The current implementation pops the
        stack at the same time as the floating point value is loaded to a
        temporary register. This will corrupt the state of the x87 stack if
        the store fails. This changeset introduces a pop87 micro-instruction
        that pops the stack and uses this instruction in the affected
        macro-instructions to pop the stack after storing the value to memory.

diffstat:

 
src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
 |  6 ++++--
 src/arch/x86/isa/microops/fpop.isa                                             
         |  9 +++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diffs (38 lines):

diff -r 0063c7dd18ec -r 5924b77fb8fc 
src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
--- 
a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
   Mon Sep 30 09:53:52 2013 +0200
+++ 
b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
   Mon Sep 30 11:51:25 2013 +0200
@@ -69,13 +69,15 @@
 };
 
 def macroop FSTP_M {
-    movfp ufp1, st(0), spm=1
+    movfp ufp1, st(0)
     stfp ufp1, seg, sib, disp
+    pop87
 };
 
 def macroop FSTP_P {
-    movfp ufp1, st(0), spm=1
+    movfp ufp1, st(0)
     rdip t7
     stfp ufp1, seg, riprel, disp
+    pop87
 };
 '''
diff -r 0063c7dd18ec -r 5924b77fb8fc src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa        Mon Sep 30 09:53:52 2013 +0200
+++ b/src/arch/x86/isa/microops/fpop.isa        Mon Sep 30 11:51:25 2013 +0200
@@ -411,4 +411,13 @@
     class chsfp(FpUnaryOp):
         code = 'FpDestReg = (-1) * (FpSrcReg1);'
         flag_code = 'FSW = FSW & (~CC1Bit);'
+
+    class Pop87(FpUnaryOp):
+        def __init__(self, spm=1, UpdateFTW=True):
+            super(Pop87, self).__init__(               \
+                    "InstRegIndex(FLOATREG_MICROFP0)", \
+                    "InstRegIndex(FLOATREG_MICROFP0)", \
+                    spm=spm, SetStatus=False, UpdateFTW=UpdateFTW)
+
+        code = ''
 }};
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