changeset 2935441b0870 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2935441b0870
description:
x86: Add support for m5ops through a memory mapped interface
In order to support m5ops in virtualized environments, we need to use
a memory mapped interface. This changeset adds support for that by
reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR
interface for m5ops. The mapping is done in the
X86ISA::TLB::finalizePhysical() which means that it just works for all
of the CPU models, including virtualized ones.
diffstat:
configs/common/FSConfig.py | 5 ++++-
src/arch/x86/tlb.cc | 8 ++++++++
util/m5/Makefile.x86 | 2 +-
util/m5/m5.c | 27 +++++++++++++++++++++++++++
util/m5/m5op_x86.S | 20 ++++++++++++++++++++
5 files changed, 60 insertions(+), 2 deletions(-)
diffs (151 lines):
diff -r e105fbf799e7 -r 2935441b0870 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Mon Sep 30 12:20:43 2013 +0200
+++ b/configs/common/FSConfig.py Mon Sep 30 12:20:53 2013 +0200
@@ -509,7 +509,10 @@
# Mark the rest as available
X86E820Entry(addr = 0x100000,
size = '%dB' % (phys_mem_size - 0x100000),
- range_type = 1)
+ range_type = 1),
+ # Reserve the last 16kB of the 32-bit address space for the
+ # m5op interface
+ X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
]
# Command line
diff -r e105fbf799e7 -r 2935441b0870 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Mon Sep 30 12:20:43 2013 +0200
+++ b/src/arch/x86/tlb.cc Mon Sep 30 12:20:53 2013 +0200
@@ -39,6 +39,7 @@
#include <cstring>
+#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/msr.hh"
@@ -237,6 +238,8 @@
AddrRange apicRange(localApicBase.base * PageBytes,
(localApicBase.base + 1) * PageBytes - 1);
+ AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
+
if (apicRange.contains(paddr)) {
// The Intel developer's manuals say the below restrictions apply,
// but the linux kernel, because of a compiler optimization, breaks
@@ -253,6 +256,11 @@
req->setFlags(Request::UNCACHEABLE);
req->setPaddr(x86LocalAPICAddress(tc->contextId(),
paddr - apicRange.start()));
+ } else if (m5opRange.contains(paddr)) {
+ req->setFlags(Request::MMAPPED_IPR);
+ req->setPaddr(GenericISA::iprAddressPseudoInst(
+ (paddr >> 8) & 0xFF,
+ paddr & 0xFF));
}
}
diff -r e105fbf799e7 -r 2935441b0870 util/m5/Makefile.x86
--- a/util/m5/Makefile.x86 Mon Sep 30 12:20:43 2013 +0200
+++ b/util/m5/Makefile.x86 Mon Sep 30 12:20:53 2013 +0200
@@ -31,7 +31,7 @@
AS=as
LD=ld
-CFLAGS=-O2
+CFLAGS=-O2 -DM5OP_ADDR=0xFFFF0000
OBJS=m5.o m5op_x86.o
all: m5
diff -r e105fbf799e7 -r 2935441b0870 util/m5/m5.c
--- a/util/m5/m5.c Mon Sep 30 12:20:43 2013 +0200
+++ b/util/m5/m5.c Mon Sep 30 12:20:53 2013 +0200
@@ -51,10 +51,15 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
#include <unistd.h>
#include "m5op.h"
+void *m5_mem = NULL;
+
char *progname;
char *command = "unspecified";
void usage();
@@ -315,6 +320,26 @@
exit(1);
}
+static void
+map_m5_mem()
+{
+#ifdef M5OP_ADDR
+ int fd;
+
+ fd = open("/dev/mem", O_RDWR | O_SYNC);
+ if (fd == -1) {
+ perror("Can't open /dev/mem");
+ exit(1);
+ }
+
+ m5_mem = mmap(NULL, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd,
M5OP_ADDR);
+ if (!m5_mem) {
+ perror("Can't mmap /dev/mem");
+ exit(1);
+ }
+#endif
+}
+
int
main(int argc, char *argv[])
{
@@ -322,6 +347,8 @@
if (argc < 2)
usage(1);
+ map_m5_mem();
+
command = argv[1];
argv += 2;
diff -r e105fbf799e7 -r 2935441b0870 util/m5/m5op_x86.S
--- a/util/m5/m5op_x86.S Mon Sep 30 12:20:43 2013 +0200
+++ b/util/m5/m5op_x86.S Mon Sep 30 12:20:53 2013 +0200
@@ -32,6 +32,24 @@
#include "m5ops.h"
+#ifdef M5OP_ADDR
+/* Use the memory mapped m5op interface */
+#define TWO_BYTE_OP(name, number) \
+ .globl name; \
+ .func name; \
+name: \
+ mov m5_mem, %r11; \
+ mov $number, %rax; \
+ shl $8, %rax; \
+ mov 0(%r11, %rax, 1), %rax; \
+ ret; \
+ .endfunc;
+
+#else
+/* Use the magic instruction based m5op interface. This does not work
+ * in virtualized environments.
+ */
+
#define TWO_BYTE_OP(name, number) \
.globl name; \
.func name; \
@@ -41,6 +59,8 @@
ret; \
.endfunc;
+#endif
+
TWO_BYTE_OP(arm, arm_func)
TWO_BYTE_OP(quiesce, quiesce_func)
TWO_BYTE_OP(quiesceNs, quiescens_func)
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