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(Updated Oct. 8, 2013, 1:42 p.m.) Review request for Default. Changes ------- 1) Commented some more 2) Undid the attempt to pass lower bits to lower level caches 3) Made parameters const Repository: gem5 Description ------- Extends the classic prefetcher. This patch, originally started by Amin Farmahini, extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean). Diffs (updated) ----- src/mem/cache/prefetch/stride.cc 8bddb3879c16 src/mem/cache/prefetch/base.cc 8bddb3879c16 src/mem/cache/prefetch/base.hh 8bddb3879c16 src/mem/cache/prefetch/Prefetcher.py 8bddb3879c16 src/mem/cache/cache_impl.hh 8bddb3879c16 src/mem/request.hh 8bddb3879c16 Diff: http://reviews.gem5.org/r/2000/diff/ Testing ------- Benchmarked SPEC2006 simpoints, will post on the dev mailing list with more detailed results. Thanks, Mitch Hayenga _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
