Hi folks, I've been working on re-doing the integration between Gem5 and SST.
The basic idea is to have SST provide the memory hierarchy (caches, main memory, etc) to processor cores that are provided by Gem5. I've created an "External Connector" MemObject that provides a mechanism for SST to connect into Gem5, and translate Gem5 Memory Packets to and from SST's MemEvent. Through this mechanism, I've been able to successfully boot Linux on an x86 Full-System configuration with SST-provided memory hierarchy. However, I'm currently running into an issue with the Full-System Pseudo Instructions for m5readfile, in that it causes Functional accesses to the memory hierarchy, both through the TLB Walker cache, as well as the the data cache. Functional accesses don't integrate well with SST, as it is a pure timing based simulation environment. If I set the system's MemoryMode to Timing (or, alternatively, a new mode "External"), then we should avoid Functional accesses all together. I had previously solved this in our old port with Gem5 for SE mode's system call emulation, by causing the instruction pointer not to advance until the system call had completed. This was fairly easy in the context of system call emulation, but I'm not sure that the same technique would work well in the general Pseudo-instruction context. Does anybody have advice on how we can cleanly get these Pseudo-Instruction's functional accesses to switch to Timing-based Accesses? Thanks much, - Branden -- Branden J. Moore Sandia National Labs (505) 844-0989 [email protected] _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
