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Review request for Default. Repository: gem5 Description ------- Changeset 9923:d621cbc86079 --------------------------- mem: Just-in-time write scheduling in DRAM controller This patch removes the untimed while loop in the write scheduling mechanism and now schedule commands taking into account the minimum timing constraint. It also introduces an optimization to track write queue size and switch from writes to reads if the number of write requests fall below write low threshold. Diffs ----- src/mem/SimpleDRAM.py 3de4393f5649 src/mem/simple_dram.hh 3de4393f5649 src/mem/simple_dram.cc 3de4393f5649 Diff: http://reviews.gem5.org/r/2052/diff/ Testing ------- All regressions pass (with stats update) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
