changeset 7f43babfde6a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7f43babfde6a
description:
cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.
diffstat:
src/arch/arm/insts/misc.cc | 12 ++--
src/arch/arm/insts/static_inst.cc | 23 ++++++---
src/arch/power/insts/static_inst.cc | 30 +++++++----
src/arch/x86/insts/static_inst.cc | 55 +++++++++++++--------
src/cpu/SConscript | 1 +
src/cpu/checker/cpu_impl.hh | 25 +++++++--
src/cpu/inorder/cpu.cc | 68 ++++++++++++++++++---------
src/cpu/inorder/cpu.hh | 15 ++++-
src/cpu/inorder/inorder_dyn_inst.cc | 47 ++++++++++++------
src/cpu/o3/dyn_inst.hh | 22 ++++++--
src/cpu/o3/rename_impl.hh | 34 ++++++++++---
src/cpu/reg_class.cc | 37 ++++++++++++++
src/cpu/reg_class.hh | 92 +++++++++++++++++++++++++++++++++++++
13 files changed, 352 insertions(+), 109 deletions(-)
diffs (truncated from 831 to 300 lines):
diff -r 3de4393f5649 -r 7f43babfde6a src/arch/arm/insts/misc.cc
--- a/src/arch/arm/insts/misc.cc Tue Oct 15 13:26:34 2013 +0200
+++ b/src/arch/arm/insts/misc.cc Tue Oct 15 14:22:42 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +39,7 @@
*/
#include "arch/arm/insts/misc.hh"
+#include "cpu/reg_class.hh"
std::string
MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -48,17 +50,17 @@
ss << ", ";
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
- int idx = srcRegIdx(i);
- if (idx < Ctrl_Base_DepTag) {
+ RegIndex idx = srcRegIdx(i);
+ RegIndex rel_idx;
+ if (regIdxToClass(idx, &rel_idx) != MiscRegClass) {
continue;
}
- idx -= Ctrl_Base_DepTag;
- if (idx == MISCREG_CPSR) {
+ if (rel_idx == MISCREG_CPSR) {
ss << "cpsr";
foundPsr = true;
break;
}
- if (idx == MISCREG_SPSR) {
+ if (rel_idx == MISCREG_SPSR) {
ss << "spsr";
foundPsr = true;
break;
diff -r 3de4393f5649 -r 7f43babfde6a src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Tue Oct 15 13:26:34 2013 +0200
+++ b/src/arch/arm/insts/static_inst.cc Tue Oct 15 14:22:42 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -45,6 +46,7 @@
#include "base/loader/symtab.hh"
#include "base/condcodes.hh"
#include "base/cprintf.hh"
+#include "cpu/reg_class.hh"
namespace ArmISA
{
@@ -208,8 +210,11 @@
void
ArmStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
- switch (reg) {
+ RegIndex rel_reg;
+
+ switch (regIdxToClass(reg, &rel_reg)) {
+ case IntRegClass:
+ switch (rel_reg) {
case PCReg:
ccprintf(os, "pc");
break;
@@ -226,12 +231,14 @@
ccprintf(os, "r%d", reg);
break;
}
- } else if (reg < Ctrl_Base_DepTag) {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
- } else {
- reg -= Ctrl_Base_DepTag;
- assert(reg < NUM_MISCREGS);
- ccprintf(os, "%s", ArmISA::miscRegName[reg]);
+ break;
+ case FloatRegClass:
+ ccprintf(os, "f%d", rel_reg);
+ break;
+ case MiscRegClass:
+ assert(rel_reg < NUM_MISCREGS);
+ ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
+ break;
}
}
diff -r 3de4393f5649 -r 7f43babfde6a src/arch/power/insts/static_inst.cc
--- a/src/arch/power/insts/static_inst.cc Tue Oct 15 13:26:34 2013 +0200
+++ b/src/arch/power/insts/static_inst.cc Tue Oct 15 14:22:42 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,23 +30,30 @@
*/
#include "arch/power/insts/static_inst.hh"
+#include "cpu/reg_class.hh"
using namespace PowerISA;
void
PowerStaticInst::printReg(std::ostream &os, int reg) const
{
- if (reg < FP_Base_DepTag) {
- ccprintf(os, "r%d", reg);
- } else if (reg < Ctrl_Base_DepTag) {
- ccprintf(os, "f%d", reg - FP_Base_DepTag);
- } else {
- switch (reg - Ctrl_Base_DepTag) {
- case 0: ccprintf(os, "cr"); break;
- case 1: ccprintf(os, "xer"); break;
- case 2: ccprintf(os, "lr"); break;
- case 3: ccprintf(os, "ctr"); break;
- default: ccprintf(os, "unknown_reg");
+ RegIndex rel_reg;
+
+ switch (regIdxToClass(reg, &rel_reg)) {
+ case IntRegClass:
+ ccprintf(os, "r%d", rel_reg);
+ break;
+ case FloatRegClass:
+ ccprintf(os, "f%d", rel_reg);
+ break;
+ case MiscRegClass:
+ switch (rel_reg) {
+ case 0: ccprintf(os, "cr"); break;
+ case 1: ccprintf(os, "xer"); break;
+ case 2: ccprintf(os, "lr"); break;
+ case 3: ccprintf(os, "ctr"); break;
+ default: ccprintf(os, "unknown_reg");
+ break;
}
}
}
diff -r 3de4393f5649 -r 7f43babfde6a src/arch/x86/insts/static_inst.cc
--- a/src/arch/x86/insts/static_inst.cc Tue Oct 15 13:26:34 2013 +0200
+++ b/src/arch/x86/insts/static_inst.cc Tue Oct 15 14:22:42 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -39,6 +40,7 @@
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/regs/segment.hh"
+#include "cpu/reg_class.hh"
namespace X86ISA
{
@@ -129,17 +131,20 @@
static const char * microFormats[9] =
{"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
- if (reg < FP_Base_DepTag) {
+ RegIndex rel_reg;
+
+ switch (regIdxToClass(reg, &rel_reg)) {
+ case IntRegClass: {
const char * suffix = "";
- bool fold = reg & IntFoldBit;
- reg &= ~IntFoldBit;
+ bool fold = rel_reg & IntFoldBit;
+ rel_reg &= ~IntFoldBit;
if(fold)
suffix = "h";
- else if(reg < 8 && size == 1)
+ else if(rel_reg < 8 && size == 1)
suffix = "l";
- switch (reg) {
+ switch (rel_reg) {
case INTREG_RAX:
ccprintf(os, abcdFormats[size], "a");
break;
@@ -189,33 +194,39 @@
ccprintf(os, longFormats[size], "15");
break;
default:
- ccprintf(os, microFormats[size], reg - NUM_INTREGS);
+ ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS);
}
ccprintf(os, suffix);
- } else if (reg < Ctrl_Base_DepTag) {
- int fpindex = reg - FP_Base_DepTag;
- if(fpindex < NumMMXRegs) {
- ccprintf(os, "%%mmx%d", reg - FP_Base_DepTag);
+ break;
+ }
+
+ case FloatRegClass: {
+ if (rel_reg < NumMMXRegs) {
+ ccprintf(os, "%%mmx%d", rel_reg);
return;
}
- fpindex -= NumMMXRegs;
- if(fpindex < NumXMMRegs * 2) {
- ccprintf(os, "%%xmm%d_%s", fpindex / 2,
- (fpindex % 2) ? "high": "low");
+ rel_reg -= NumMMXRegs;
+ if (rel_reg < NumXMMRegs * 2) {
+ ccprintf(os, "%%xmm%d_%s", rel_reg / 2,
+ (rel_reg % 2) ? "high": "low");
return;
}
- fpindex -= NumXMMRegs * 2;
- if(fpindex < NumMicroFpRegs) {
- ccprintf(os, "%%ufp%d", fpindex);
+ rel_reg -= NumXMMRegs * 2;
+ if (rel_reg < NumMicroFpRegs) {
+ ccprintf(os, "%%ufp%d", rel_reg);
return;
}
- fpindex -= NumMicroFpRegs;
- ccprintf(os, "%%st(%d)", fpindex);
- } else {
- switch (reg - Ctrl_Base_DepTag) {
+ rel_reg -= NumMicroFpRegs;
+ ccprintf(os, "%%st(%d)", rel_reg);
+ break;
+ }
+
+ case MiscRegClass:
+ switch (rel_reg) {
default:
- ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
+ ccprintf(os, "%%ctrl%d", rel_reg);
}
+ break;
}
}
diff -r 3de4393f5649 -r 7f43babfde6a src/cpu/SConscript
--- a/src/cpu/SConscript Tue Oct 15 13:26:34 2013 +0200
+++ b/src/cpu/SConscript Tue Oct 15 14:22:42 2013 -0400
@@ -118,6 +118,7 @@
Source('pc_event.cc')
Source('profile.cc')
Source('quiesce_event.cc')
+Source('reg_class.cc')
Source('static_inst.cc')
Source('simple_thread.cc')
Source('thread_context.cc')
diff -r 3de4393f5649 -r 7f43babfde6a src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Tue Oct 15 13:26:34 2013 +0200
+++ b/src/cpu/checker/cpu_impl.hh Tue Oct 15 14:22:42 2013 -0400
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,6 +51,7 @@
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "cpu/reg_class.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
@@ -597,13 +599,17 @@
// so do the fix-up then start with the next dest reg;
if (start_idx >= 0) {
RegIndex idx = inst->destRegIdx(start_idx);
- if (idx < TheISA::FP_Base_DepTag) {
+ switch (regIdxToClass(idx)) {
+ case IntRegClass:
thread->setIntReg(idx, mismatch_val);
- } else if (idx < TheISA::Ctrl_Base_DepTag) {
+ break;
+ case FloatRegClass:
thread->setFloatRegBits(idx, mismatch_val);
- } else if (idx < TheISA::Max_DepTag) {
+ break;
+ case MiscRegClass:
thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
mismatch_val);
+ break;
}
}
start_idx++;
@@ -611,14 +617,19 @@
for (int i = start_idx; i < inst->numDestRegs(); i++) {
RegIndex idx = inst->destRegIdx(i);
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