changeset 028e4da64b42 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=028e4da64b42
description:
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
diffstat:
src/arch/SConscript | 3 +-
src/arch/alpha/isa.hh | 7 ++
src/arch/alpha/registers.hh | 7 ++-
src/arch/alpha/utility.cc | 3 +
src/arch/arm/insts/static_inst.cc | 2 +
src/arch/arm/isa.hh | 7 ++
src/arch/arm/registers.hh | 7 ++-
src/arch/arm/utility.cc | 11 ++-
src/arch/isa_parser.py | 81 ++++++++++++++++++++++++++++++++++
src/arch/mips/isa.hh | 7 ++
src/arch/mips/registers.hh | 7 ++-
src/arch/null/registers.hh | 1 +
src/arch/power/insts/static_inst.cc | 2 +
src/arch/power/isa.hh | 7 ++
src/arch/power/registers.hh | 7 ++-
src/arch/power/utility.cc | 3 +
src/arch/sparc/isa.hh | 7 ++
src/arch/sparc/registers.hh | 10 +++-
src/arch/sparc/utility.cc | 3 +
src/arch/x86/insts/static_inst.cc | 4 +
src/arch/x86/isa.hh | 6 ++
src/arch/x86/registers.hh | 5 +-
src/arch/x86/utility.cc | 2 +
src/cpu/base_dyn_inst.hh | 7 ++
src/cpu/checker/cpu.hh | 14 +++++
src/cpu/checker/cpu_impl.hh | 6 ++
src/cpu/checker/thread_context.hh | 17 +++++++
src/cpu/inorder/cpu.cc | 32 +++++++++++++
src/cpu/inorder/cpu.hh | 8 +++
src/cpu/inorder/inorder_dyn_inst.cc | 4 +
src/cpu/inorder/inorder_dyn_inst.hh | 9 +++
src/cpu/inorder/thread_context.cc | 31 +++++++++++++
src/cpu/inorder/thread_context.hh | 11 ++++
src/cpu/o3/O3CPU.py | 1 +
src/cpu/o3/cpu.cc | 88 +++++++++++++++++++++++++++++++++++-
src/cpu/o3/cpu.hh | 11 ++++
src/cpu/o3/dyn_inst.hh | 18 +++++++
src/cpu/o3/free_list.cc | 2 +
src/cpu/o3/free_list.hh | 24 +++++++++-
src/cpu/o3/inst_queue.hh | 7 +--
src/cpu/o3/inst_queue_impl.hh | 8 +-
src/cpu/o3/regfile.cc | 25 ++++++++-
src/cpu/o3/regfile.hh | 57 ++++++++++++++++++++++-
src/cpu/o3/rename_impl.hh | 14 +++++-
src/cpu/o3/rename_map.cc | 11 ++++
src/cpu/o3/rename_map.hh | 35 ++++++++++++++
src/cpu/o3/thread_context.hh | 13 +++++
src/cpu/o3/thread_context_impl.hh | 24 ++++++++++
src/cpu/ozone/cpu_impl.hh | 19 +++++++
src/cpu/reg_class.cc | 1 +
src/cpu/reg_class.hh | 9 +++-
src/cpu/simple/base.cc | 13 +++++
src/cpu/simple/base.hh | 20 ++++++++
src/cpu/simple_thread.hh | 53 ++++++++++++++++++++++
src/cpu/static_inst.hh | 4 +
src/cpu/thread_context.cc | 23 +++++++++
src/cpu/thread_context.hh | 24 ++++++++++
57 files changed, 806 insertions(+), 36 deletions(-)
diffs (truncated from 2264 to 300 lines):
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/SConscript
--- a/src/arch/SConscript Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/SConscript Tue Oct 15 14:22:44 2013 -0400
@@ -135,5 +135,6 @@
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
+DebugFlag('CCRegs')
DebugFlag('MiscRegs')
-CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/alpha/isa.hh Tue Oct 15 14:22:44 2013 -0400
@@ -103,6 +103,13 @@
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
const Params *params() const;
ISA(Params *p);
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/alpha/registers.hh
--- a/src/arch/alpha/registers.hh Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/alpha/registers.hh Tue Oct 15 14:22:44 2013 -0400
@@ -53,6 +53,9 @@
// control register file contents
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
union AnyReg
{
IntReg intreg;
@@ -91,6 +94,7 @@
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
+const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs =
@@ -101,7 +105,8 @@
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
FP_Reg_Base = NumIntRegs,
- Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/alpha/utility.cc
--- a/src/arch/alpha/utility.cc Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/alpha/utility.cc Tue Oct 15 14:22:44 2013 -0400
@@ -71,6 +71,9 @@
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegBits(i, src->readFloatRegBits(i));
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
// Copy misc. registers
copyMiscRegs(src, dest);
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/arm/insts/static_inst.cc Tue Oct 15 14:22:44 2013 -0400
@@ -239,6 +239,8 @@
assert(rel_reg < NUM_MISCREGS);
ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
break;
+ case CCRegClass:
+ panic("printReg: CCRegClass but ARM has no CC regs\n");
}
}
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/arm/isa.hh Tue Oct 15 14:22:44 2013 -0400
@@ -140,6 +140,13 @@
return reg;
}
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
+ return reg;
+ }
+
int
flattenMiscIndex(int reg)
{
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/arm/registers.hh
--- a/src/arch/arm/registers.hh Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/arm/registers.hh Tue Oct 15 14:22:44 2013 -0400
@@ -68,6 +68,9 @@
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
+// dummy typedef since we don't have CC regs
+typedef uint8_t CCReg;
+
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
@@ -76,6 +79,7 @@
const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -102,7 +106,8 @@
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
-const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/arm/utility.cc Tue Oct 15 14:22:44 2013 -0400
@@ -113,7 +113,7 @@
void
skipFunction(ThreadContext *tc)
{
- TheISA::PCState newPC = tc->pcState();
+ PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
CheckerCPU *checker = tc->getCheckerCpuPtr();
@@ -127,13 +127,16 @@
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
- for (int i = 0; i < TheISA::NumIntRegs; i++)
+ for (int i = 0; i < NumIntRegs; i++)
dest->setIntRegFlat(i, src->readIntRegFlat(i));
- for (int i = 0; i < TheISA::NumFloatRegs; i++)
+ for (int i = 0; i < NumFloatRegs; i++)
dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
- for (int i = 0; i < TheISA::NumMiscRegs; i++)
+ // Would need to add condition-code regs if implemented
+ assert(NumCCRegs == 0);
+
+ for (int i = 0; i < NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
// setMiscReg "with effect" will set the misc register mapping correctly.
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/isa_parser.py
--- a/src/arch/isa_parser.py Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/isa_parser.py Tue Oct 15 14:22:44 2013 -0400
@@ -1,4 +1,5 @@
# Copyright (c) 2003-2005 The Regents of The University of Michigan
+# Copyright (c) 2013 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -497,6 +498,9 @@
def isIntReg(self):
return 0
+ def isCCReg(self):
+ return 0
+
def isControlReg(self):
return 0
@@ -660,6 +664,79 @@
}''' % (self.ctype, self.base_name, wp)
return wb
+class CCRegOperand(Operand):
+ def isReg(self):
+ return 1
+
+ def isCCReg(self):
+ return 1
+
+ def makeConstructor(self, predRead, predWrite):
+ c_src = ''
+ c_dest = ''
+
+ if self.is_src:
+ c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + CC_Reg_Base;' % \
+ (self.reg_spec)
+ if self.hasReadPred():
+ c_src = '\n\tif (%s) {%s\n\t}' % \
+ (self.read_predicate, c_src)
+
+ if self.is_dest:
+ c_dest = \
+ '\n\t_destRegIdx[_numDestRegs++] = %s + CC_Reg_Base;' % \
+ (self.reg_spec)
+ c_dest += '\n\t_numCCDestRegs++;'
+ if self.hasWritePred():
+ c_dest = '\n\tif (%s) {%s\n\t}' % \
+ (self.write_predicate, c_dest)
+
+ return c_src + c_dest
+
+ def makeRead(self, predRead):
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error('Attempt to read condition-code register as FP')
+ if self.read_code != None:
+ return self.buildReadCode('readCCRegOperand')
+
+ int_reg_val = ''
+ if predRead:
+ int_reg_val = 'xc->readCCRegOperand(this, _sourceIndex++)'
+ if self.hasReadPred():
+ int_reg_val = '(%s) ? %s : 0' % \
+ (self.read_predicate, int_reg_val)
+ else:
+ int_reg_val = 'xc->readCCRegOperand(this, %d)' % self.src_reg_idx
+
+ return '%s = %s;\n' % (self.base_name, int_reg_val)
+
+ def makeWrite(self, predWrite):
+ if (self.ctype == 'float' or self.ctype == 'double'):
+ error('Attempt to write condition-code register as FP')
+ if self.write_code != None:
+ return self.buildWriteCode('setCCRegOperand')
+
+ if predWrite:
+ wp = 'true'
+ if self.hasWritePred():
+ wp = self.write_predicate
+
+ wcond = 'if (%s)' % (wp)
+ windex = '_destIndex++'
+ else:
+ wcond = ''
+ windex = '%d' % self.dest_reg_idx
+
+ wb = '''
+ %s
+ {
+ %s final_val = %s;
+ xc->setCCRegOperand(this, %s, final_val);\n
+ if (traceData) { traceData->setData(final_val); }
+ }''' % (wcond, self.ctype, self.base_name, windex)
+
+ return wb
+
class ControlRegOperand(Operand):
def isReg(self):
return 1
@@ -815,6 +892,7 @@
self.numDestRegs = 0
self.numFPDestRegs = 0
self.numIntDestRegs = 0
+ self.numCCDestRegs = 0
self.numMiscDestRegs = 0
self.memOperand = None
@@ -835,6 +913,8 @@
self.numFPDestRegs += 1
elif op_desc.isIntReg():
self.numIntDestRegs += 1
+ elif op_desc.isCCReg():
+ self.numCCDestRegs += 1
elif op_desc.isControlReg():
self.numMiscDestRegs += 1
elif op_desc.isMem():
@@ -1030,6 +1110,7 @@
header += '\n\t_numDestRegs = 0;'
header += '\n\t_numFPDestRegs = 0;'
header += '\n\t_numIntDestRegs = 0;'
+ header += '\n\t_numCCDestRegs = 0;'
self.constructor = header + \
self.operands.concatAttrStrings('constructor')
diff -r 803903a8dac1 -r 028e4da64b42 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Tue Oct 15 14:22:44 2013 -0400
+++ b/src/arch/mips/isa.hh Tue Oct 15 14:22:44 2013 -0400
@@ -177,6 +177,13 @@
{
return reg;
}
+
+ // dummy
+ int
+ flattenCCIndex(int reg)
+ {
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