changeset 2efeed2cef09 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2efeed2cef09
description:
cpu: Fix O3 uncacheable load that is replayed but misses the TLB
This change fixes an issue in the O3 CPU where an uncachable instruction
is attempted to be executed before it reaches the head of the ROB. It is
determined to be uncacheable, and is replayed, but a PanicFault is
attached
to the instruction to make sure that it is properly executed before
committing. If the TLB entry it was using is replaced in the
interveaning
time, the TLB returns a delayed translation when the load is replayed at
the head of the ROB, however the LSQ code can't differntiate between the
old fault and the new one. If the translation isn't complete it can't
be faulting, so clear the fault.
diffstat:
src/cpu/base_dyn_inst.hh | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diffs (35 lines):
diff -r 086fc5c038af -r 2efeed2cef09 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/base_dyn_inst.hh Thu Oct 17 10:20:45 2013 -0500
@@ -1009,8 +1009,16 @@
// One translation if the request isn't split.
DataTranslation<BaseDynInstPtr> *trans =
new DataTranslation<BaseDynInstPtr>(this, state);
+
cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
+
if (!translationCompleted()) {
+ // The translation isn't yet complete, so we can't possibly have a
+ // fault. Overwrite any existing fault we might have from a
previous
+ // execution of this instruction (e.g. an uncachable load that
+ // couldn't execute because it wasn't at the head of the ROB).
+ fault = NoFault;
+
// Save memory requests.
savedReq = state->mainReq;
savedSreqLow = state->sreqLow;
@@ -1028,7 +1036,14 @@
cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
+
if (!translationCompleted()) {
+ // The translation isn't yet complete, so we can't possibly have a
+ // fault. Overwrite any existing fault we might have from a
previous
+ // execution of this instruction (e.g. an uncachable load that
+ // couldn't execute because it wasn't at the head of the ROB).
+ fault = NoFault;
+
// Save memory requests.
savedReq = state->mainReq;
savedSreqLow = state->sreqLow;
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