changeset 4ff1c5c6dcbc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4ff1c5c6dcbc
description:
cpu: add consistent guarding to *_impl.hh files.
diffstat:
src/cpu/base_dyn_inst_impl.hh | 5 +++++
src/cpu/checker/cpu_impl.hh | 5 +++++
src/cpu/o3/commit_impl.hh | 4 ++++
src/cpu/o3/decode_impl.hh | 5 +++++
src/cpu/o3/dyn_inst_impl.hh | 4 ++++
src/cpu/o3/fetch_impl.hh | 5 +++++
src/cpu/o3/iew_impl.hh | 5 +++++
src/cpu/o3/inst_queue_impl.hh | 5 +++++
src/cpu/o3/lsq_impl.hh | 5 +++++
src/cpu/o3/lsq_unit_impl.hh | 5 +++++
src/cpu/o3/mem_dep_unit_impl.hh | 5 +++++
src/cpu/o3/rename_impl.hh | 5 +++++
src/cpu/o3/rob_impl.hh | 5 +++++
src/cpu/o3/thread_context_impl.hh | 4 ++++
src/cpu/ozone/back_end_impl.hh | 5 +++++
src/cpu/ozone/cpu_impl.hh | 5 +++++
src/cpu/ozone/dyn_inst_impl.hh | 5 +++++
src/cpu/ozone/front_end_impl.hh | 4 ++++
src/cpu/ozone/inorder_back_end_impl.hh | 4 ++++
src/cpu/ozone/inst_queue_impl.hh | 5 +++++
src/cpu/ozone/lsq_unit_impl.hh | 3 +++
src/cpu/ozone/lw_back_end_impl.hh | 3 +++
src/cpu/ozone/lw_lsq_impl.hh | 5 +++++
src/cpu/ozone/rename_table_impl.hh | 4 ++++
src/cpu/pred/bpred_unit_impl.hh | 5 +++++
src/mem/cache/cache_impl.hh | 5 +++++
26 files changed, 120 insertions(+), 0 deletions(-)
diffs (truncated from 490 to 300 lines):
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/base_dyn_inst_impl.hh
--- a/src/cpu/base_dyn_inst_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/base_dyn_inst_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
+#define __CPU_BASE_DYN_INST_IMPL_HH__
+
#include <iostream>
#include <set>
#include <sstream>
@@ -228,3 +231,5 @@
return true;
}
+
+#endif//__CPU_BASE_DYN_INST_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/checker/cpu_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -42,6 +42,9 @@
* Geoffrey Blake
*/
+#ifndef __CPU_CHECKER_CPU_IMPL_HH__
+#define __CPU_CHECKER_CPU_IMPL_HH__
+
#include <list>
#include <string>
@@ -684,3 +687,5 @@
}
}
+
+#endif//__CPU_CHECKER_CPU_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/commit_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,8 @@
* Authors: Kevin Lim
* Korey Sewell
*/
+#ifndef __CPU_O3_COMMIT_IMPL_HH__
+#define __CPU_O3_COMMIT_IMPL_HH__
#include <algorithm>
#include <set>
@@ -1540,3 +1542,5 @@
return InvalidThreadID;
}
}
+
+#endif//__CPU_O3_COMMIT_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/decode_impl.hh
--- a/src/cpu/o3/decode_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/decode_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_O3_DECODE_IMPL_HH__
+#define __CPU_O3_DECODE_IMPL_HH__
+
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
@@ -767,3 +770,5 @@
wroteToTimeBuffer = true;
}
}
+
+#endif//__CPU_O3_DECODE_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/dyn_inst_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_O3_DYN_INST_IMPL_HH__
+#define __CPU_O3_DYN_INST_IMPL_HH__
+
#include "base/cp_annotate.hh"
#include "cpu/o3/dyn_inst.hh"
#include "sim/full_system.hh"
@@ -255,3 +258,4 @@
}
}
+#endif//__CPU_O3_DYN_INST_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/fetch_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -41,6 +41,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_FETCH_IMPL_HH__
+#define __CPU_O3_FETCH_IMPL_HH__
+
#include <algorithm>
#include <cstring>
#include <list>
@@ -1631,3 +1634,5 @@
tid, fetchStatus[tid]);
}
}
+
+#endif//__CPU_O3_FETCH_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/iew_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_O3_IEW_IMPL_IMPL_HH__
+#define __CPU_O3_IEW_IMPL_IMPL_HH__
+
// @todo: Fix the instantaneous communication among all the stages within
// iew. There's a clear delay between issue and execute, yet backwards
// communication happens simultaneously.
@@ -1671,3 +1674,5 @@
}
}
}
+
+#endif//__CPU_O3_IEW_IMPL_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/inst_queue_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -42,6 +42,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
+#define __CPU_O3_INST_QUEUE_IMPL_HH__
+
#include <limits>
#include <vector>
@@ -1508,3 +1511,5 @@
++num;
}
}
+
+#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/lsq_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Korey Sewell
*/
+#ifndef __CPU_O3_LSQ_IMPL_HH__
+#define __CPU_O3_LSQ_IMPL_HH__
+
#include <algorithm>
#include <list>
#include <string>
@@ -658,3 +661,5 @@
thread[tid].dumpInsts();
}
}
+
+#endif//__CPU_O3_LSQ_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -42,6 +42,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
+#define __CPU_O3_LSQ_UNIT_IMPL_HH__
+
#include "arch/generic/debugfaults.hh"
#include "arch/locked_mem.hh"
#include "base/str.hh"
@@ -1289,3 +1292,5 @@
cprintf("\n");
}
+
+#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/mem_dep_unit_impl.hh
--- a/src/cpu/o3/mem_dep_unit_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/mem_dep_unit_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -40,6 +40,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
+
#include <map>
#include "cpu/o3/inst_queue.hh"
@@ -594,3 +597,5 @@
cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
#endif
}
+
+#endif//__CPU_O3_MEM_DEP_UNIT_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/rename_impl.hh
--- a/src/cpu/o3/rename_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/rename_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -42,6 +42,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_RENAME_IMPL_HH__
+#define __CPU_O3_RENAME_IMPL_HH__
+
#include <list>
#include "arch/isa_traits.hh"
@@ -1383,3 +1386,5 @@
}
}
}
+
+#endif//__CPU_O3_RENAME_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/rob_impl.hh
--- a/src/cpu/o3/rob_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/rob_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -41,6 +41,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_ROB_IMPL_HH__
+#define __CPU_O3_ROB_IMPL_HH__
+
#include <list>
#include "cpu/o3/rob.hh"
@@ -560,3 +563,5 @@
}
return NULL;
}
+
+#endif//__CPU_O3_ROB_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/o3/thread_context_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -42,6 +42,9 @@
* Korey Sewell
*/
+#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
+
#include "arch/kernel_stats.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"
@@ -297,6 +300,7 @@
conditionalSquash();
}
+#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/ozone/back_end_impl.hh
--- a/src/cpu/ozone/back_end_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/ozone/back_end_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -28,6 +28,9 @@
* Authors: Kevin Lim
*/
+#ifndef __CPU_OZONE_BACK_END_IMPL_HH__
+#define __CPU_OZONE_BACK_END_IMPL_HH__
+
#include "cpu/ozone/back_end.hh"
#include "encumbered/cpu/full/op_class.hh"
@@ -1912,3 +1915,5 @@
++num;
}
}
+
+#endif//__CPU_OZONE_BACK_END_IMPL_HH__
diff -r cc1e0ea8e450 -r 4ff1c5c6dcbc src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh Thu Oct 17 10:20:45 2013 -0500
+++ b/src/cpu/ozone/cpu_impl.hh Thu Oct 17 10:20:45 2013 -0500
@@ -30,6 +30,9 @@
* Nathan Binkert
*/
+#ifndef __CPU_OZONE_CPU_IMPL_HH__
+#define __CPU_OZONE_CPU_IMPL_HH__
+
#include "arch/alpha/osfpal.hh"
#include "arch/isa_traits.hh" // For MachInst
#include "arch/kernel_stats.hh"
@@ -868,6 +871,8 @@
}
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