----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2060/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 9866:03a35785a047 --------------------------- cpu: Fix O3 issuse with load+barrier instructions. Fix a problem in the O3 CPU for instructions that are both memory loads and memory barriers (e.g. load acquire) and to uncacheable memory. This combination can confuse the commit stage into commitng an instruction that hasn't executed and got it's value yet. At the same time refactor the code slightly to remove duplication between two of the cases. Diffs ----- src/cpu/o3/commit_impl.hh 13ffc0066b76 Diff: http://reviews.gem5.org/r/2060/diff/ Testing ------- Thanks, Ali Saidi _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
