> On Oct. 25, 2013, 2:40 a.m., Amin Farmahini wrote: > > One suggestion: if streaming requests to the same row and same bank arrive > > with an interval bigger than tBURST, they are delayed by tCL. But in fact, > > they should be delayed by max(tCCD, tBURST) which is lower than tCL. I > > would guess this situation does not happen much with processors. However, > > LOW frequency IO devices which are directly connected to DRAM suffer from > > this. > > Please let me give you an example with DDR3: If requests to the same rank, > > same row, and same bank arrive with a period of 10ns (the time internval > > between two consecutive requests is 10ns), data for each request should be > > transfered with a delay of max(tCCD, tBURST)=5.0ns. However, in the current > > code, that delay is equal to tCL which 13.75ns. > > Please let me know if I am missing something because I am no expert.
You're observation is absolutely right Amin. A fixed gap between arrivals does not guarantee a fixed gap between scheduling and finishing, even if tCCD and tBURST would (in theory) allow it. This is due to how the absolute time of the arrival interacts with tCL and the alignment between the two. Thus, if you keep sending requests every 10 ns, some of them will finish 5 ns (tBURST) apart, and some will finish 13.75 ns (tCL) apart, depending on if the bank ended up being considered "free" before the last arrival. Overall this effect should be negligible, and I would suggest we keep things as is for now. In the end, the serviced rate should still be one every 10 ns. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2045/#review4793 ----------------------------------------------------------- On Oct. 16, 2013, 7:39 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2045/ > ----------------------------------------------------------- > > (Updated Oct. 16, 2013, 7:39 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9916:e254040a4aa0 > --------------------------- > mem: Fix DRAM bank occupancy for streaming access > > This patch fixes an issue that allowed more than 100% bus utilisation > in certain cases. > > > Diffs > ----- > > src/mem/simple_dram.cc 3de4393f5649 > > Diff: http://reviews.gem5.org/r/2045/diff/ > > > Testing > ------- > > All regressions pass (with stats update) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
