changeset a01cc09ae34c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a01cc09ae34c
description:
mem: Fix DRAM bank occupancy for streaming access
This patch fixes an issue that allowed more than 100% bus utilisation
in certain cases.
diffstat:
src/mem/simple_dram.cc | 14 ++++++++++----
1 files changed, 10 insertions(+), 4 deletions(-)
diffs (27 lines):
diff -r 6da4081bcbb4 -r a01cc09ae34c src/mem/simple_dram.cc
--- a/src/mem/simple_dram.cc Fri Nov 01 11:56:17 2013 -0400
+++ b/src/mem/simple_dram.cc Fri Nov 01 11:56:18 2013 -0400
@@ -957,13 +957,19 @@
// but do care about bank being free for access
rowHitFlag = true;
- if (bank.freeAt < inTime) {
+ // When a series of requests arrive to the same row,
+ // DDR systems are capable of streaming data continuously
+ // at maximum bandwidth (subject to tCCD). Here, we approximate
+ // this condition, and assume that if whenever a bank is already
+ // busy and a new request comes in, it can be completed with no
+ // penalty beyond waiting for the existing read to complete.
+ if (bank.freeAt > inTime) {
+ accLat += bank.freeAt - inTime;
+ bankLat += tBURST;
+ } else {
// CAS latency only
accLat += tCL;
bankLat += tCL;
- } else {
- accLat += 0;
- bankLat += 0;
}
} else {
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