changeset 31591b699509 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=31591b699509
description:
mem: Fix for 100% write threshold in DRAM controller
This patch fixes the controller when a write threshold of 100% is
used. Earlier for 100% write threshold no data is written to memory
as writes never get triggered since this corner case is not
considered.
diffstat:
src/mem/simple_dram.cc | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r 1ef53e046ca0 -r 31591b699509 src/mem/simple_dram.cc
--- a/src/mem/simple_dram.cc Fri Nov 01 11:56:20 2013 -0400
+++ b/src/mem/simple_dram.cc Fri Nov 01 11:56:21 2013 -0400
@@ -563,7 +563,7 @@
accessAndRespond(pkt, frontendLatency);
// If your write buffer is starting to fill up, drain it!
- if (writeQueue.size() > writeThreshold && !stopReads){
+ if (writeQueue.size() >= writeThreshold && !stopReads){
triggerWrites();
}
}
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