changeset cb786bfbd1ea in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cb786bfbd1ea
description:
mem: Less conservative tRAS in DRAM configurations
This patch changes the default values of the tRAS timing parameter to
be less conservative, and closer in line with existing parts.
diffstat:
src/mem/SimpleDRAM.py | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diffs (44 lines):
diff -r 8053f651a089 -r cb786bfbd1ea src/mem/SimpleDRAM.py
--- a/src/mem/SimpleDRAM.py Fri Nov 01 11:56:22 2013 -0400
+++ b/src/mem/SimpleDRAM.py Fri Nov 01 11:56:23 2013 -0400
@@ -168,11 +168,11 @@
# DDR3 has 8 banks in all configurations
banks_per_rank = 8
- # DDR3-1600 11-11-11
+ # DDR3-1600 11-11-11-28
tRCD = '13.75ns'
tCL = '13.75ns'
tRP = '13.75ns'
- tRAS = '41.25ns'
+ tRAS = '35ns'
# 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
# Note this is a BL8 DDR device.
@@ -224,7 +224,7 @@
# Pre-charge one bank 15 ns (all banks 18 ns)
tRP = '15ns'
- tRAS = '45ns'
+ tRAS = '42ns'
# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
# Note this is a BL8 DDR device.
@@ -269,7 +269,7 @@
tRCD = '18ns'
tCL = '18ns'
tRP = '18ns'
- tRAS = '54ns'
+ tRAS = '42ns'
# 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
# Note this is a BL4 SDR device.
@@ -317,7 +317,7 @@
# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
tCL = '15ns'
- tRAS = '45ns'
+ tRAS = '42ns'
# Pre-charge one bank 15 ns (all banks 18 ns)
tRP = '15ns'
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