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(Updated Nov. 4, 2013, 9:44 a.m.) Review request for Default. Changes ------- A mistake made in LRU::accessBlock function. The "lat" parameter has to be passed by reference (not by value). Sorry... Repository: gem5 Description ------- This patch allows specifying different cache latency for read and write access. (In the code, the hit_latency parameter is actually the read_latency) Diffs (updated) ----- src/mem/cache/BaseCache.py 07352f119e48 src/mem/cache/base.hh 07352f119e48 src/mem/cache/base.cc 07352f119e48 src/mem/cache/cache_impl.hh 07352f119e48 src/mem/cache/tags/lru.cc 07352f119e48 Diff: http://reviews.gem5.org/r/2072/diff/ Testing ------- I used --debug-flags command to check read hit latency and write hit latency for Dcache and Icache. I checked the time between a request sent by the cpu and the response sent by the cache memory. Thanks, Sophiane SENNI _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
