[gem5-dev] changeset in gem5: x86: Implementation of Int3 and Int_Ib in lon...

[Christian Menard]

changeset d70124a5d594 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d70124a5d594
description:
        x86: Implementation of Int3 and Int_Ib in long mode

        This is an implementation of the x86 int3 and int immediate
        instructions for long mode according to 'AMD64 Programmers Manual
        Volume 3'.

diffstat:

 src/arch/x86/isa/decoder/one_byte_opcodes.isa                                  
      |   6 +-
 
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
 |  28 ++++++++++
 2 files changed, 32 insertions(+), 2 deletions(-)

diffs (61 lines):

diff -r 94b8d1af6c81 -r d70124a5d594 
src/arch/x86/isa/decoder/one_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa     Tue Nov 26 17:40:58 
2013 +0100
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa     Tue Nov 26 17:51:07 
2013 +0100
@@ -393,8 +393,8 @@
                     0x3, 0x4: ret_far_real();
                     default: Inst::RET_FAR();
                 }
-                0x4: int3();
-                0x5: decode FullSystemInt default int_Ib() {
+                0x4: Inst::INT3();
+                0x5: decode FullSystemInt default inst_ib() {
                     0: decode IMMEDIATE {
                         // Really only the LSB matters, but the decoder
                         // will sign extend it, and there's no easy way to
@@ -403,6 +403,8 @@
                             SyscallInst::int80('xc->syscall(Rax)',
                                  IsSyscall, IsNonSpeculative, 
IsSerializeAfter);
                     }
+
+                    default: Inst::INT(Ib);
                 }
                 0x6: decode MODE_SUBMODE {
                     0x0: Inst::UD2();
diff -r 94b8d1af6c81 -r d70124a5d594 
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
--- 
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
      Tue Nov 26 17:40:58 2013 +0100
+++ 
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
      Tue Nov 26 17:51:07 2013 +0100
@@ -221,6 +221,34 @@
 def macroop IRET_VIRT {
     panic "Virtual mode iret isn't implemented!"
 };
+
+def macroop INT3 {
+
+    limm t1, 0x03, dataSize=8
+
+    rdip t7
+
+    # Are we in long mode?
+    rdm5reg t5
+    andi t0, t5, 0x1, flags=(EZF,)
+    br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+    br rom_label("legacyModeInterrupt")
+};
+
+def macroop INT_I {
+
+    #load the byte-sized interrupt vector specified in the instruction
+    .adjust_imm trimImm(8)
+    limm t1, imm, dataSize=8
+
+    rdip t7
+
+    # Are we in long mode?
+    rdm5reg t5
+    andi t0, t5, 0x1, flags=(EZF,)
+    br rom_label("longModeSoftInterrupt"), flags=(CEZF,)
+    br rom_label("legacyModeInterrupt")
+};
 '''
 #let {{
 #    class INT(Inst):
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