> On Dec. 18, 2013, 2:21 p.m., Erfan Azarkhish wrote: > > Dear Andreas, > > > > I tried to apply the patch, however I faced the following problems: > > > > 1. Class system does not have any member cacheLineSize() > > build/ARM_DRAM/mem/dramsim2.cc: In member function 'virtual void > > DRAMSim2::init()': > > build/ARM_DRAM/mem/dramsim2.cc:86:19: error: 'class System' has no member > > named 'cacheLineSize' > > build/ARM_DRAM/mem/dramsim2.cc:87:9: error: 'class System' has no member > > named 'cacheLineSize' > > scons: *** [build/ARM_DRAM/mem/dramsim2.fo] Error 1 > > > > 2. The parameter which should be passed to fs.py is DRAMSim2 and not > > dramsim2 (ext/dramsim2/README) > > > > fs.py: error: option --mem-type: invalid choice: '=' (choose from > > 'LPDDR2_S4_1066_x32', 'WideIO_200_x128', 'LPDDR3_1600_x32', 'DRAMSim2', > > 'DDR3_1600_x64', 'SimpleMemory', 'SimpleDRAM', 'lpddr2_s4_1066_x32', > > 'wio_200_x128', 'lpddr3_1600_x32', 'dramsim2', 'ddr3_1600_x64', > > 'simple_mem') > >
1. Are you using an up-to-date version of gem5? The cache line size was added a while back. 2. Concerning the type, both DRAMSim2 (the class name) and dramsim2 (the alias) should work. It seems your problem is with the formatting of your command line as it is complaining that you chose '='. Could you double check? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2087/#review4844 ----------------------------------------------------------- On Nov. 14, 2013, 6:24 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2087/ > ----------------------------------------------------------- > > (Updated Nov. 14, 2013, 6:24 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9981:02da0086461e > --------------------------- > mem: Add a wrapped DRAMSim2 memory controller > > This patch adds DRAMSim2 as a memory controller by wrapping the > external library and creating a sublass of AbstractMemory that bridges > between the semantics of gem5 and the DRAMSim2 interface. > > The DRAMSim2 wrapper extracts the clock period from the config > file. There is no way of extracting this information from DRAMSim2 > itself, so we simply read the same config file and get it from there. > > To properly model the response queue, the wrapper keeps track of how > many transactions are in the actual controller, and how many are > stacking up waiting to be sent back as responses (in the wrapper). The > latter requires us to move away from the queued port and manage the > packets ourselves. This is due to DRAMSim2 not having any flow control > on the response path. > > DRAMSim2 assumes that the transactions it is given are matching the > burst size of the choosen memory. The wrapper checks to ensure the > cache line size of the system matches the burst size of DRAMSim2 as > there are currently no provisions to split the system requests. In > theory we could allow a cache line size smaller than the burst size, > but that would lead to inefficient use of the DRAM, so for not we > fatal also in this case. > > > Diffs > ----- > > .hgignore 329b8a20958b > SConstruct 329b8a20958b > configs/common/MemConfig.py 329b8a20958b > ext/dramsim2/README PRE-CREATION > ext/dramsim2/SConscript PRE-CREATION > src/mem/DRAMSim2.py PRE-CREATION > src/mem/SConscript 329b8a20958b > src/mem/dramsim2.hh PRE-CREATION > src/mem/dramsim2.cc PRE-CREATION > src/mem/dramsim2_wrapper.hh PRE-CREATION > src/mem/dramsim2_wrapper.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/2087/diff/ > > > Testing > ------- > > Ran a bunch of regressions and other test cases making use of the > wrapper. > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
