Hi, everyone! I read the code about the memory controller in ruby system and have some questions about it.
I want to calculate the bandwidth of the memory controller in ruby. So I write a simple test program, in which I malloc 1MB memory and read 1byte every 64byte(the cacheline size). As I know, the memory controller transmit data to or receive data from the LLC(last level cache) by cacheline size(64 bytes). So I can think memory controller transmit 1MB data in my program. Is this right? If this is right, there is something wrong. Because the bandwidth I calculated is exceeding the theoritical value 3.2GB/s. Or, the frequency of memory controller is set 400MHz meaning that the bandwidth is 400M*64byte=25.6GB/s, not 400M*64bit=3.2GB/s !!! Besides, what's the following configuration parameter meaning and where can the values of them be refered? bank_busy_time mem_ctl_latency As I know, the DDR-400 has the core frequency 200MHz, and the Trcd-Trp-CL is 3-3-3, is this the bank_busy_time? If so, the bank_busy_time should be set to 18, not 11. Any answers is appreciated! Thanks! [email protected] _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
