changeset a362694dda2d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a362694dda2d
description:
ruby: remove unused label no_vector
diffstat:
src/mem/protocol/MESI_Two_Level-dma.sm | 8 ++++----
src/mem/protocol/MI_example-dma.sm | 8 ++++----
src/mem/protocol/MOESI_CMP_token-dma.sm | 8 ++++----
src/mem/protocol/MOESI_hammer-dma.sm | 8 ++++----
4 files changed, 16 insertions(+), 16 deletions(-)
diffs (100 lines):
diff -r 2e9e2fb2fa71 -r a362694dda2d src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.sm Fri Jan 10 16:19:58 2014 -0600
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm Fri Jan 17 11:02:15 2014 -0600
@@ -32,8 +32,8 @@
Cycles request_latency = 6
{
- MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request", no_vector="true";
+ MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
+ MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request";
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -53,8 +53,8 @@
void dataCallback(DataBlock);
}
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
+ MessageBuffer mandatoryQueue, ordered="false";
+ State cur_state;
State getState(Address addr) {
return cur_state;
diff -r 2e9e2fb2fa71 -r a362694dda2d src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Fri Jan 10 16:19:58 2014 -0600
+++ b/src/mem/protocol/MI_example-dma.sm Fri Jan 17 11:02:15 2014 -0600
@@ -32,8 +32,8 @@
Cycles request_latency = 6
{
- MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request", no_vector="true";
+ MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
+ MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request";
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -48,8 +48,8 @@
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
+ MessageBuffer mandatoryQueue, ordered="false";
+ State cur_state;
State getState(Address addr) {
return cur_state;
diff -r 2e9e2fb2fa71 -r a362694dda2d src/mem/protocol/MOESI_CMP_token-dma.sm
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm Fri Jan 10 16:19:58 2014 -0600
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Fri Jan 17 11:02:15 2014 -0600
@@ -32,8 +32,8 @@
Cycles request_latency = 6
{
- MessageBuffer responseFromDir, network="From", virtual_network="5",
ordered="true", vnet_type="response", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request", no_vector="true";
+ MessageBuffer responseFromDir, network="From", virtual_network="5",
ordered="true", vnet_type="response";
+ MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request";
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -53,8 +53,8 @@
void dataCallback(DataBlock);
}
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
+ MessageBuffer mandatoryQueue, ordered="false";
+ State cur_state;
State getState(Address addr) {
return cur_state;
diff -r 2e9e2fb2fa71 -r a362694dda2d src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm Fri Jan 10 16:19:58 2014 -0600
+++ b/src/mem/protocol/MOESI_hammer-dma.sm Fri Jan 17 11:02:15 2014 -0600
@@ -32,8 +32,8 @@
Cycles request_latency = 6
{
- MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request", no_vector="true";
+ MessageBuffer responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
+ MessageBuffer reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request";
state_declaration(State,
desc="DMA states",
@@ -50,8 +50,8 @@
Ack, desc="DMA write to memory completed";
}
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
+ MessageBuffer mandatoryQueue, ordered="false";
+ State cur_state;
State getState(Address addr) {
return cur_state;
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