changeset 2f33cb012383 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2f33cb012383
description:
mem: track per-request latencies and access depths in the cache
hierarchy
Add some values and methods to the request object to track the
translation
and access latency for a request and which level of the cache hierarchy
responded
to the request.
diffstat:
src/cpu/o3/fetch_impl.hh | 1 +
src/cpu/o3/lsq_unit_impl.hh | 2 +
src/cpu/simple/timing.cc | 6 ++++-
src/cpu/translation.hh | 1 +
src/mem/cache/base.hh | 2 +-
src/mem/request.hh | 46 ++++++++++++++++++++++++++++++++++++++++++++-
6 files changed, 55 insertions(+), 3 deletions(-)
diffs (165 lines):
diff -r a14f92150d3f -r 2f33cb012383 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:29 2014 -0600
+++ b/src/cpu/o3/fetch_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -400,6 +400,7 @@
fetchStatus[tid] = IcacheAccessComplete;
}
+ pkt->req->setAccessLatency();
// Reset the mem req to NULL.
delete pkt->req;
delete pkt;
diff -r a14f92150d3f -r 2f33cb012383 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Fri Jan 24 15:29:29 2014 -0600
+++ b/src/cpu/o3/lsq_unit_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -129,6 +129,8 @@
delete state->mainPkt->req;
delete state->mainPkt;
}
+
+ pkt->req->setAccessLatency();
delete state;
delete pkt->req;
delete pkt;
diff -r a14f92150d3f -r 2f33cb012383 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Fri Jan 24 15:29:29 2014 -0600
+++ b/src/cpu/simple/timing.cc Fri Jan 24 15:29:30 2014 -0600
@@ -646,7 +646,6 @@
// received a response from the icache: execute the received
// instruction
-
assert(!pkt || !pkt->isError());
assert(_status == IcacheWaitResponse);
@@ -655,6 +654,10 @@
numCycles += curCycle() - previousCycle;
previousCycle = curCycle();
+ if (pkt)
+ pkt->req->setAccessLatency();
+
+
preExecute();
if (curStaticInst && curStaticInst->isMemRef()) {
// load or store: just send to dcache
@@ -749,6 +752,7 @@
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
+ pkt->req->setAccessLatency();
numCycles += curCycle() - previousCycle;
previousCycle = curCycle();
diff -r a14f92150d3f -r 2f33cb012383 src/cpu/translation.hh
--- a/src/cpu/translation.hh Fri Jan 24 15:29:29 2014 -0600
+++ b/src/cpu/translation.hh Fri Jan 24 15:29:30 2014 -0600
@@ -256,6 +256,7 @@
assert(mode == state->mode);
if (state->finish(fault, index)) {
xc->finishTranslation(state);
+ req->setTranslateLatency();
}
delete this;
}
diff -r a14f92150d3f -r 2f33cb012383 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Fri Jan 24 15:29:29 2014 -0600
+++ b/src/mem/cache/base.hh Fri Jan 24 15:29:30 2014 -0600
@@ -568,7 +568,7 @@
{
assert(pkt->req->masterId() < system->maxMasters());
misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
-
+ pkt->req->incAccessDepth();
if (missCount) {
--missCount;
if (missCount == 0)
diff -r a14f92150d3f -r 2f33cb012383 src/mem/request.hh
--- a/src/mem/request.hh Fri Jan 24 15:29:29 2014 -0600
+++ b/src/mem/request.hh Fri Jan 24 15:29:30 2014 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -244,6 +244,7 @@
* default constructor.)
*/
Request()
+ : translateDelta(0), accessDelta(0), depth(0)
{}
/**
@@ -304,6 +305,9 @@
_flags.set(flags);
privateFlags.clear(~STICKY_PRIVATE_FLAGS);
privateFlags.set(VALID_PADDR|VALID_SIZE);
+ depth = 0;
+ accessDelta = 0;
+ //translateDelta = 0;
}
void
@@ -331,6 +335,9 @@
_flags.set(flags);
privateFlags.clear(~STICKY_PRIVATE_FLAGS);
privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
+ depth = 0;
+ accessDelta = 0;
+ translateDelta = 0;
}
/**
@@ -382,6 +389,23 @@
}
/**
+ * Time for the TLB/table walker to successfully translate this request.
+ */
+ Tick translateDelta;
+
+ /**
+ * Access latency to complete this memory transaction not including
+ * translation time.
+ */
+ Tick accessDelta;
+
+ /**
+ * Level of the cache hierachy where this request was responded to
+ * (e.g. 0 = L1; 1 = L2).
+ */
+ int depth;
+
+ /**
* Accessor for size.
*/
bool
@@ -535,6 +559,26 @@
return _pc;
}
+ /**
+ * Increment/Get the depth at which this request is responded to.
+ * This currently happens when the request misses in any cache level.
+ */
+ void incAccessDepth() { depth++; }
+ int getAccessDepth() const { return depth; }
+
+ /**
+ * Set/Get the time taken for this request to be successfully translated.
+ */
+ void setTranslateLatency() { translateDelta = curTick() - _time; }
+ Tick getTranslateLatency() const { return translateDelta; }
+
+ /**
+ * Set/Get the time taken to complete this request's access, not including
+ * the time to successfully translate the request.
+ */
+ void setAccessLatency() { accessDelta = curTick() - _time -
translateDelta; }
+ Tick getAccessLatency() const { return accessDelta; }
+
/** Accessor functions for flags. Note that these are for testing
only; setting flags should be done via setFlags(). */
bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
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